97540 lines
3.9 MiB
97540 lines
3.9 MiB
<?xml version="1.0" encoding="UTF-8"?>
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<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<vendor>Freescale Semiconductor, Inc.</vendor>
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<vendorID>Freescale</vendorID>
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<series>Kinetis_E</series>
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<name>MKE15Z7</name>
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<version>1.6</version>
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<description>MKE15Z7 Freescale Microcontroller</description>
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<licenseText>Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</licenseText>
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<cpu>
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<name>CM0PLUS</name>
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<revision>r0p0</revision>
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<endian>little</endian>
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<fpuPresent>false</fpuPresent>
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<mpuPresent>false</mpuPresent>
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<vtorPresent>true</vtorPresent>
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<nvicPrioBits>2</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<peripherals>
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<peripheral>
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<name>FTFE_FlashConfig</name>
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<description>Flash configuration field</description>
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<prependToName>NV_</prependToName>
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<baseAddress>0x400</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x10</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>BACKKEY3</name>
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<description>Backdoor Comparison Key 3.</description>
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<addressOffset>0</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY2</name>
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<description>Backdoor Comparison Key 2.</description>
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<addressOffset>0x1</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY1</name>
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<description>Backdoor Comparison Key 1.</description>
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<addressOffset>0x2</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY0</name>
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<description>Backdoor Comparison Key 0.</description>
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<addressOffset>0x3</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY7</name>
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<description>Backdoor Comparison Key 7.</description>
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<addressOffset>0x4</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY6</name>
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<description>Backdoor Comparison Key 6.</description>
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<addressOffset>0x5</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY5</name>
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<description>Backdoor Comparison Key 5.</description>
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<addressOffset>0x6</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>BACKKEY4</name>
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<description>Backdoor Comparison Key 4.</description>
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<addressOffset>0x7</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>KEY</name>
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<description>Backdoor Comparison Key.</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT3</name>
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<description>Non-volatile P-Flash Protection 1 - Low Register</description>
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<addressOffset>0x8</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT2</name>
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<description>Non-volatile P-Flash Protection 1 - High Register</description>
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<addressOffset>0x9</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT1</name>
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<description>Non-volatile P-Flash Protection 0 - Low Register</description>
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<addressOffset>0xA</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FPROT0</name>
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<description>Non-volatile P-Flash Protection 0 - High Register</description>
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<addressOffset>0xB</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>PROT</name>
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<description>P-Flash Region Protect</description>
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<bitOffset>0</bitOffset>
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<bitWidth>8</bitWidth>
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<access>read-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>FSEC</name>
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<description>Non-volatile Flash Security Register</description>
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<addressOffset>0xC</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0xFF</resetValue>
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<resetMask>0xFF</resetMask>
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<fields>
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<field>
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<name>SEC</name>
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<description>Flash Security</description>
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<bitOffset>0</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>10</name>
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<description>MCU security status is unsecure</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>11</name>
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<description>MCU security status is secure</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>FSLACC</name>
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<description>Freescale Failure Analysis Access Code</description>
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<bitOffset>2</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>10</name>
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<description>Freescale factory access denied</description>
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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|
<name>11</name>
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<description>Freescale factory access granted</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>MEEN</name>
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<description>no description available</description>
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<bitOffset>4</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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|
<name>10</name>
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<description>Mass erase is disabled</description>
|
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
|
|
<name>11</name>
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<description>Mass erase is enabled</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>KEYEN</name>
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<description>Backdoor Key Security Enable</description>
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<bitOffset>6</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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<enumeratedValue>
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<name>10</name>
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<description>Backdoor key access enabled</description>
|
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<value>#10</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>11</name>
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<description>Backdoor key access disabled</description>
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<value>#11</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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<register>
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<name>FOPT</name>
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<description>Non-volatile Flash Option Register</description>
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<addressOffset>0xD</addressOffset>
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<size>8</size>
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<access>read-only</access>
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<resetValue>0x7D</resetValue>
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<resetMask>0xFF</resetMask>
|
|
<fields>
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<field>
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<name>LPBOOT</name>
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<description>no description available</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>00</name>
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<description>Low-power boot</description>
|
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<value>#0</value>
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</enumeratedValue>
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|
<enumeratedValue>
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|
<name>01</name>
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<description>Normal boot</description>
|
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<value>#1</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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|
<field>
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<name>BOOTPIN_OPT</name>
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<description>no description available</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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<enumeratedValues>
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|
<enumeratedValue>
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|
<name>00</name>
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<description>Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin</description>
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<value>#0</value>
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</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Boot source configured by FOPT (BOOTSRC_SEL) bits</description>
|
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<value>#1</value>
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</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NMI_DIS</name>
|
|
<description>no description available</description>
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<bitOffset>2</bitOffset>
|
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<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>NMI interrupts are always blocked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>NMI_b pin/interrupts reset default to enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAST_INIT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Slower initialization</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fast Initialization</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOOTSRC_SEL</name>
|
|
<description>Boot source selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Boot from Flash</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Boot from ROM</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Boot from ROM</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEPROT</name>
|
|
<description>Non-volatile EERAM Protection Register</description>
|
|
<addressOffset>0xE</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPROT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDPROT</name>
|
|
<description>Non-volatile D-Flash Protection Register</description>
|
|
<addressOffset>0xF</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DPROT</name>
|
|
<description>D-Flash Region Protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>AIPS</name>
|
|
<description>AIPS-Lite Bridge</description>
|
|
<prependToName>AIPS_</prependToName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x84</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MPRA</name>
|
|
<description>Master Privilege Register A</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MPL2</name>
|
|
<description>Master 2 Privilege Level</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW2</name>
|
|
<description>Master 2 Trusted For Writes</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR2</name>
|
|
<description>Master 2 Trusted For Read</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MPL0</name>
|
|
<description>Master 0 Privilege Level</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from this master are forced to user-mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from this master are not forced to user-mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTW0</name>
|
|
<description>Master 0 Trusted For Writes</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for write accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MTR0</name>
|
|
<description>Master 0 Trusted For Read</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This master is not trusted for read accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This master is trusted for read accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B,C,D</dimIndex>
|
|
<name>PACR%s</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>16</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P</dimIndex>
|
|
<name>OPACR%s</name>
|
|
<description>Off-Platform Peripheral Access Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP7</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP7</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP7</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP6</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP6</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP6</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP5</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP5</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP4</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP4</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP3</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP3</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP2</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP2</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PACRU</name>
|
|
<description>Peripheral Access Control Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TP1</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP1</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TP0</name>
|
|
<description>Trusted Protect</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Accesses from an untrusted master are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Accesses from an untrusted master are not allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Write Protect</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral allows write accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral is write protected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SP0</name>
|
|
<description>Supervisor Protect</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This peripheral does not require supervisor privilege level for accesses.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This peripheral requires supervisor privilege level for accesses.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA</name>
|
|
<description>Enhanced direct memory access controller</description>
|
|
<prependToName>DMA_</prependToName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1100</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA0_04</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_15</name>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_26</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_37</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA_Error</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDBG</name>
|
|
<description>Enable Debug</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When in debug mode, the DMA continues to operate.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERCA</name>
|
|
<description>Enable Round Robin Channel Arbitration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fixed priority arbitration is used for channel selection .</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Round robin arbitration is used for channel selection .</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HOE</name>
|
|
<description>Halt On Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HALT</name>
|
|
<description>Halt DMA Operations</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLM</name>
|
|
<description>Continuous Link Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A minor loop channel link made to itself goes through channel arbitration before being activated again.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMLM</name>
|
|
<description>Enable Minor Loop Mapping</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECX</name>
|
|
<description>Error Cancel Transfer</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CX</name>
|
|
<description>Cancel Transfer</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>DMA Active Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>eDMA is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>eDMA is executing a channel.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ES</name>
|
|
<description>Error Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBE</name>
|
|
<description>Destination Bus Error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No destination bus error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a bus error on a destination write</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBE</name>
|
|
<description>Source Bus Error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No source bus error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a bus error on a source read</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SGE</name>
|
|
<description>Scatter/Gather Configuration Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No scatter/gather configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NCE</name>
|
|
<description>NBYTES/CITER Configuration Error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No NBYTES/CITER configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOE</name>
|
|
<description>Destination Offset Error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No destination offset configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DAE</name>
|
|
<description>Destination Address Error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No destination address configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOE</name>
|
|
<description>Source Offset Error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No source offset configuration error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAE</name>
|
|
<description>Source Address Error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No source address configuration error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERRCHN</name>
|
|
<description>Error Channel Number or Canceled Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CPE</name>
|
|
<description>Channel Priority Error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel priority error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECX</name>
|
|
<description>Transfer Canceled</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No canceled transfers</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last recorded entry was a canceled transfer by the error cancel transfer input</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VLD</name>
|
|
<description>Logical OR of all ERR status bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No ERR bits are set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one ERR bit is set indicating a valid error exists that has not been cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERQ</name>
|
|
<description>Enable Request Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERQ0</name>
|
|
<description>Enable DMA Request 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ1</name>
|
|
<description>Enable DMA Request 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ2</name>
|
|
<description>Enable DMA Request 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ3</name>
|
|
<description>Enable DMA Request 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ4</name>
|
|
<description>Enable DMA Request 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ5</name>
|
|
<description>Enable DMA Request 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ6</name>
|
|
<description>Enable DMA Request 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERQ7</name>
|
|
<description>Enable DMA Request 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The DMA request signal for the corresponding channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The DMA request signal for the corresponding channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEI</name>
|
|
<description>Enable Error Interrupt Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EEI0</name>
|
|
<description>Enable Error Interrupt 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI1</name>
|
|
<description>Enable Error Interrupt 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI2</name>
|
|
<description>Enable Error Interrupt 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI3</name>
|
|
<description>Enable Error Interrupt 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI4</name>
|
|
<description>Enable Error Interrupt 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI5</name>
|
|
<description>Enable Error Interrupt 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI6</name>
|
|
<description>Enable Error Interrupt 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EEI7</name>
|
|
<description>Enable Error Interrupt 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The error signal for corresponding channel does not generate an error interrupt</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The assertion of the error signal for corresponding channel generates an error interrupt request</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CEEI</name>
|
|
<description>Clear Enable Error Interrupt Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEEI</name>
|
|
<description>Clear Enable Error Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAEE</name>
|
|
<description>Clear All Enable Error Interrupts</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear only the EEI bit specified in the CEEI field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear all bits in EEI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEEI</name>
|
|
<description>Set Enable Error Interrupt Register</description>
|
|
<addressOffset>0x19</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEEI</name>
|
|
<description>Set Enable Error Interrupt</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SAEE</name>
|
|
<description>Sets All Enable Error Interrupts</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set only the EEI bit specified in the SEEI field.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sets all bits in EEI</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CERQ</name>
|
|
<description>Clear Enable Request Register</description>
|
|
<addressOffset>0x1A</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CERQ</name>
|
|
<description>Clear Enable Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAER</name>
|
|
<description>Clear All Enable Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear only the ERQ bit specified in the CERQ field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear all bits in ERQ</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SERQ</name>
|
|
<description>Set Enable Request Register</description>
|
|
<addressOffset>0x1B</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SERQ</name>
|
|
<description>Set Enable Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SAER</name>
|
|
<description>Set All Enable Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set only the ERQ bit specified in the SERQ field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set all bits in ERQ</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDNE</name>
|
|
<description>Clear DONE Status Bit Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CDNE</name>
|
|
<description>Clear DONE Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CADN</name>
|
|
<description>Clears All DONE Bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clears only the TCDn_CSR[DONE] bit specified in the CDNE field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clears all bits in TCDn_CSR[DONE]</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSRT</name>
|
|
<description>Set START Bit Register</description>
|
|
<addressOffset>0x1D</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSRT</name>
|
|
<description>Set START Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SAST</name>
|
|
<description>Set All START Bits (activates all channels)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set only the TCDn_CSR[START] bit specified in the SSRT field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set all bits in TCDn_CSR[START]</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CERR</name>
|
|
<description>Clear Error Register</description>
|
|
<addressOffset>0x1E</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CERR</name>
|
|
<description>Clear Error Indicator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAEI</name>
|
|
<description>Clear All Error Indicators</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear only the ERR bit specified in the CERR field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear all bits in ERR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CINT</name>
|
|
<description>Clear Interrupt Request Register</description>
|
|
<addressOffset>0x1F</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CINT</name>
|
|
<description>Clear Interrupt Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAIR</name>
|
|
<description>Clear All Interrupt Requests</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clear only the INT bit specified in the CINT field</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear all bits in INT</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOP</name>
|
|
<description>No Op enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>No operation, ignore the other bits in this register</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<description>Interrupt Request Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INT0</name>
|
|
<description>Interrupt Request 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT1</name>
|
|
<description>Interrupt Request 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT2</name>
|
|
<description>Interrupt Request 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT3</name>
|
|
<description>Interrupt Request 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT4</name>
|
|
<description>Interrupt Request 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT5</name>
|
|
<description>Interrupt Request 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT6</name>
|
|
<description>Interrupt Request 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT7</name>
|
|
<description>Interrupt Request 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The interrupt request for corresponding channel is cleared</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The interrupt request for corresponding channel is active</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERR</name>
|
|
<description>Error Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERR0</name>
|
|
<description>Error In Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR1</name>
|
|
<description>Error In Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR2</name>
|
|
<description>Error In Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR3</name>
|
|
<description>Error In Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR4</name>
|
|
<description>Error In Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR5</name>
|
|
<description>Error In Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR6</name>
|
|
<description>Error In Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERR7</name>
|
|
<description>Error In Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>An error in this channel has not occurred</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An error in this channel has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HRS</name>
|
|
<description>Hardware Request Status Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HRS0</name>
|
|
<description>Hardware Request Status Channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for channel 0 is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for channel 0 is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS1</name>
|
|
<description>Hardware Request Status Channel 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for channel 1 is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for channel 1 is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS2</name>
|
|
<description>Hardware Request Status Channel 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for channel 2 is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for channel 2 is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS3</name>
|
|
<description>Hardware Request Status Channel 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for channel 3 is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for channel 3 is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS4</name>
|
|
<description>Hardware Request Status Channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for channel 4 is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for channel 4 is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS5</name>
|
|
<description>Hardware Request Status Channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for channel 5 is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for channel 5 is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS6</name>
|
|
<description>Hardware Request Status Channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for channel 6 is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for channel 6 is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRS7</name>
|
|
<description>Hardware Request Status Channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware service request for channel 7 is not present</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware service request for channel 7 is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EARS</name>
|
|
<description>Enable Asynchronous Request in Stop Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EDREQ_0</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 0.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable asynchronous DMA request for channel 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable asynchronous DMA request for channel 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_1</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 1.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable asynchronous DMA request for channel 1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable asynchronous DMA request for channel 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_2</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 2.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable asynchronous DMA request for channel 2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable asynchronous DMA request for channel 2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_3</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 3.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable asynchronous DMA request for channel 3.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable asynchronous DMA request for channel 3.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_4</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable asynchronous DMA request for channel 4.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable asynchronous DMA request for channel 4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_5</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable asynchronous DMA request for channel 5.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable asynchronous DMA request for channel 5.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_6</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable asynchronous DMA request for channel 6.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable asynchronous DMA request for channel 6.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EDREQ_7</name>
|
|
<description>Enable asynchronous DMA request in stop mode for channel 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable asynchronous DMA request for channel 7.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable asynchronous DMA request for channel 7.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>3,2,1,0,7,6,5,4</dimIndex>
|
|
<name>DCHPRI%s</name>
|
|
<description>Channel n Priority Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHPRI</name>
|
|
<description>Channel n Arbitration Priority</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DPA</name>
|
|
<description>Disable Preempt Ability.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel n can suspend a lower priority channel.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel n cannot suspend any channel, regardless of channel priority.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECP</name>
|
|
<description>Enable Channel Preemption.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel n cannot be suspended by a higher priority channel's service request.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel n can be temporarily suspended by the service request of a higher priority channel.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_SADDR</name>
|
|
<description>TCD Source Address</description>
|
|
<addressOffset>0x1000</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SADDR</name>
|
|
<description>Source Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_SOFF</name>
|
|
<description>TCD Signed Source Address Offset</description>
|
|
<addressOffset>0x1004</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOFF</name>
|
|
<description>Source address signed offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_ATTR</name>
|
|
<description>TCD Transfer Attributes</description>
|
|
<addressOffset>0x1006</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DSIZE</name>
|
|
<description>Destination data transfer size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMOD</name>
|
|
<description>Destination Address Modulo</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSIZE</name>
|
|
<description>Source data transfer size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>8-bit</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>16-bit</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>32-bit</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>16-byte</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>32-byte</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Source Address Modulo</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Source address modulo feature is disabled</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_NBYTES_MLNO</name>
|
|
<description>TCD Minor Byte Count (Minor Loop Mapping Disabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_NBYTES_MLOFFNO</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>30</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_NBYTES_MLOFFYES</name>
|
|
<description>TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1008</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Minor Byte Transfer Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MLOFF</name>
|
|
<description>If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMLOE</name>
|
|
<description>Destination Minor Loop Offset enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minor loop offset is not applied to the DADDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minor loop offset is applied to the DADDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMLOE</name>
|
|
<description>Source Minor Loop Offset Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minor loop offset is not applied to the SADDR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minor loop offset is applied to the SADDR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_SLAST</name>
|
|
<description>TCD Last Source Address Adjustment</description>
|
|
<addressOffset>0x100C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLAST</name>
|
|
<description>Last Source Address Adjustment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_DADDR</name>
|
|
<description>TCD Destination Address</description>
|
|
<addressOffset>0x1010</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DADDR</name>
|
|
<description>Destination Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_DOFF</name>
|
|
<description>TCD Signed Destination Address Offset</description>
|
|
<addressOffset>0x1014</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DOFF</name>
|
|
<description>Destination Address Signed Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_CITER_ELINKNO</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_CITER_ELINKYES</name>
|
|
<description>TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x1016</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CITER</name>
|
|
<description>Current Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Minor Loop Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enable channel-to-channel linking on minor-loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_DLASTSGA</name>
|
|
<description>TCD Last Destination Address Adjustment/Scatter Gather Address</description>
|
|
<addressOffset>0x1018</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLASTSGA</name>
|
|
<description>Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_CSR</name>
|
|
<description>TCD Control and Status</description>
|
|
<addressOffset>0x101C</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Channel Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel is not explicitly started.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel is explicitly started via a software initiated service request.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTMAJOR</name>
|
|
<description>Enable an interrupt when major iteration count completes.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The end-of-major loop interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The end-of-major loop interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INTHALF</name>
|
|
<description>Enable an interrupt when major counter is half complete.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The half-point interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The half-point interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DREQ</name>
|
|
<description>Disable Request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel's ERQ bit is not affected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel's ERQ bit is cleared when the major loop is complete.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESG</name>
|
|
<description>Enable Scatter/Gather Processing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The current channel's TCD is normal format.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAJORELINK</name>
|
|
<description>Enable channel-to-channel linking on major loop complete</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>Channel Active</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DONE</name>
|
|
<description>Channel Done</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJORLINKCH</name>
|
|
<description>Major Loop Link Channel Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BWC</name>
|
|
<description>Bandwidth Control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No eDMA engine stalls.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>eDMA engine stalls for 4 cycles after each R/W.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>eDMA engine stalls for 8 cycles after each R/W.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_BITER_ELINKNO</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x101E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting Major Iteration Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x20</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>TCD%s_BITER_ELINKYES</name>
|
|
<description>TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)</description>
|
|
<alternateGroup>DMA</alternateGroup>
|
|
<addressOffset>0x101E</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BITER</name>
|
|
<description>Starting major iteration count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINKCH</name>
|
|
<description>Link Channel Number</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELINK</name>
|
|
<description>Enables channel-to-channel linking on minor loop complete</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel-to-channel linking is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel-to-channel linking is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTFE</name>
|
|
<description>Flash Memory Interface</description>
|
|
<prependToName>FTFE_</prependToName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTFE</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FSTAT</name>
|
|
<description>Flash Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MGSTAT0</name>
|
|
<description>Memory Controller Command Completion Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FPVIOL</name>
|
|
<description>Flash Protection Violation Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No protection violation detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Protection violation detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACCERR</name>
|
|
<description>Flash Access Error Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No access error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Access error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDCOLERR</name>
|
|
<description>FTFE Read Collision Error Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No collision error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Collision error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIF</name>
|
|
<description>Command Complete Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTFE command or EEPROM file system operation in progress</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTFE command or EEPROM file system operation has completed</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCNFG</name>
|
|
<description>Flash Configuration Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EEERDY</name>
|
|
<description>This flag indicates if the EEPROM backup data has been copied to the FlexRAM and is therefore available for read access</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FlexRAM is not available for EEPROM operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAMRDY</name>
|
|
<description>RAM Ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FlexRAM is not available for traditional RAM access</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFLSH</name>
|
|
<description>FTFE configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTFE configuration supports one program flash blocks and one FlexNVM block</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERSSUSP</name>
|
|
<description>Erase Suspend</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No suspend requested</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Suspend the current Erase Flash Sector command execution</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ERSAREQ</name>
|
|
<description>Erase All Request</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No request or request complete</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDCOLLIE</name>
|
|
<description>Read Collision Error Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Read collision error interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CCIE</name>
|
|
<description>Command Complete Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command complete interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSEC</name>
|
|
<description>Flash Security Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEC</name>
|
|
<description>Flash Security</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>MCU security status is secure</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FSLACC</name>
|
|
<description>Freescale Failure Analysis Access Code</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Freescale factory access granted</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Freescale factory access denied</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Freescale factory access denied</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Freescale factory access granted</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MEEN</name>
|
|
<description>Mass Erase Enable Bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Mass erase is disabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Mass erase is enabled</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>KEYEN</name>
|
|
<description>Backdoor Key Security Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Backdoor key access disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Backdoor key access enabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Backdoor key access disabled</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FOPT</name>
|
|
<description>Flash Option Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OPT</name>
|
|
<description>Nonvolatile Option</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>12</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>3,2,1,0,7,6,5,4,B,A,9,8</dimIndex>
|
|
<name>FCCOB%s</name>
|
|
<description>Flash Common Command Object Registers</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCOBn</name>
|
|
<description>The FCCOB register provides a command code and relevant parameters to the memory controller</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>3,2,1,0</dimIndex>
|
|
<name>FPROT%s</name>
|
|
<description>Program Flash Protection Registers</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PROT</name>
|
|
<description>Program Flash Region Protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Program flash region is protected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Program flash region is not protected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEPROT</name>
|
|
<description>EEPROM Protection Register</description>
|
|
<addressOffset>0x16</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EPROT</name>
|
|
<description>EEPROM Region Protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>EEPROM region is protected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>EEPROM region is not protected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDPROT</name>
|
|
<description>Data Flash Protection Register</description>
|
|
<addressOffset>0x17</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DPROT</name>
|
|
<description>Data Flash Region Protect</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data Flash region is protected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data Flash region is not protected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>H3,H2,H1,H0,L3,L2,L1,L0</dimIndex>
|
|
<name>XACC%s</name>
|
|
<description>Execute-only Access Registers</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>XA</name>
|
|
<description>Execute-only access control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Associated segment is accessible in execute mode only (as an instruction fetch)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Associated segment is accessible as data or in execute mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>H3,H2,H1,H0,L3,L2,L1,L0</dimIndex>
|
|
<name>SACC%s</name>
|
|
<description>Supervisor-only Access Registers</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>Supervisor-only access control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Associated segment is accessible in supervisor mode only</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Associated segment is accessible in user or supervisor mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FACSS</name>
|
|
<description>Flash Access Segment Size Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SGSIZE</name>
|
|
<description>Segment Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FACSN</name>
|
|
<description>Flash Access Segment Number Register</description>
|
|
<addressOffset>0x2B</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NUMSG</name>
|
|
<description>Number of Segments Indicator</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>110000</name>
|
|
<description>Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes)</description>
|
|
<value>#110000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000000</name>
|
|
<description>Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes)</description>
|
|
<value>#1000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FERSTAT</name>
|
|
<description>Flash Error Status Register</description>
|
|
<addressOffset>0x2E</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFDIF</name>
|
|
<description>Double Bit Fault Detect Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Double bit fault not detected during a valid flash read access from the platform flash controller</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Double bit fault detected (or FERCNFG[FDFD] is set) during a valid flash read access from the platform flash controller</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FERCNFG</name>
|
|
<description>Flash Error Configuration Register</description>
|
|
<addressOffset>0x2F</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFDIE</name>
|
|
<description>Double Bit Fault Detect Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Double bit fault detect interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Double bit fault detect interrupt enabled. An interrupt request is generated whenever the FERSTAT[DFDIF] flag is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FDFD</name>
|
|
<description>Force Double Bit Fault Detect</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FERSTAT[DFDIF] sets only if a double bit fault is detected during read access from the platform flash controller</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FERSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt request is generated if the DFDIE bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAMUX</name>
|
|
<description>DMA channel multiplexor</description>
|
|
<prependToName>DMAMUX_</prependToName>
|
|
<baseAddress>0x40021000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x1</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>CHCFG%s</name>
|
|
<description>Channel Configuration register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOURCE</name>
|
|
<description>DMA Channel Source (Slot)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable_Signal</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TSI_Signal</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>LPUART0_Rx_Signal</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>LPUART0_Tx_Signal</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4</name>
|
|
<description>LPUART1_Rx_Signal</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5</name>
|
|
<description>LPUART1_Tx_Signal</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>LPUART2_Rx_Signal</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7</name>
|
|
<description>LPUART2_Tx_Signal</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FlexIO_Channel0_Signal</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>FlexIO_Channel1_Signal</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>12</name>
|
|
<description>FlexIO_Channel2_Signal</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>13</name>
|
|
<description>FlexIO_Channel3_Signal</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>14</name>
|
|
<description>LPSPI0_Rx_Signal</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>15</name>
|
|
<description>LPSPI0_Tx_Signal</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>16</name>
|
|
<description>LPSPI1_Rx_Signal</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>17</name>
|
|
<description>LPSPI1_Tx_Signal</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>18</name>
|
|
<description>LPI2C0_Rx_Signal</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>19</name>
|
|
<description>LPI2C0_Tx_Signal</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>20</name>
|
|
<description>FTM0_Channel0_Signal</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>21</name>
|
|
<description>FTM0_Channel1_Signal</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>22</name>
|
|
<description>FTM0_Channel2_Signal</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>23</name>
|
|
<description>FTM0_Channel3_Signal</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>24</name>
|
|
<description>FTM0_Channel4_Signal</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>25</name>
|
|
<description>FTM0_Channel5_Signal</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>26</name>
|
|
<description>FTM0_Channel6_Signal</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>27</name>
|
|
<description>FTM0_Channel7_Signal</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>28</name>
|
|
<description>FTM1_Channel0_Signal</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>29</name>
|
|
<description>FTM1_Channel1_Signal</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>30</name>
|
|
<description>FTM2_Channel0_Signal</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>31</name>
|
|
<description>FTM2_Channel1_Signal</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>32</name>
|
|
<description>LPI2C1_Rx_Signal</description>
|
|
<value>#100000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>33</name>
|
|
<description>LPI2C1_Tx_Signal</description>
|
|
<value>#100001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>40</name>
|
|
<description>ADC0_Signal</description>
|
|
<value>#101000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>41</name>
|
|
<description>ADC1_Signal</description>
|
|
<value>#101001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>43</name>
|
|
<description>CMP0_Signal</description>
|
|
<value>#101011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>44</name>
|
|
<description>CMP1_Signal</description>
|
|
<value>#101100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>46</name>
|
|
<description>PDB0_Signal</description>
|
|
<value>#101110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>49</name>
|
|
<description>PortA_Signal</description>
|
|
<value>#110001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>50</name>
|
|
<description>PortB_Signal</description>
|
|
<value>#110010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>51</name>
|
|
<description>PortC_Signal</description>
|
|
<value>#110011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>52</name>
|
|
<description>PortD_Signal</description>
|
|
<value>#110100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>53</name>
|
|
<description>PortE_Signal</description>
|
|
<value>#110101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>57</name>
|
|
<description>FTM1_Channel2_Signal</description>
|
|
<value>#111001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>58</name>
|
|
<description>FTM2_Channel2_Signal</description>
|
|
<value>#111010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>59</name>
|
|
<description>LPTMR0_Signal</description>
|
|
<value>#111011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>60</name>
|
|
<description>AlwaysOn60_Signal</description>
|
|
<value>#111100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>61</name>
|
|
<description>AlwaysOn61_Signal</description>
|
|
<value>#111101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>62</name>
|
|
<description>AlwaysOn62_Signal</description>
|
|
<value>#111110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>63</name>
|
|
<description>AlwaysOn63_Signal</description>
|
|
<value>#111111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG</name>
|
|
<description>DMA Channel Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ENBL</name>
|
|
<description>DMA Channel Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC0_</prependToName>
|
|
<baseAddress>0x4003B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xEC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC0</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>SC1%s</name>
|
|
<description>ADC Status and Control Registers 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>Input channel select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>AD0 is selected as input.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>AD1 is selected as input.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>AD2 is selected as input.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>AD3 is selected as input.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>AD4 is selected as input.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>AD5 is selected as input.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>AD6 is selected as input.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>AD7 is selected as input.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>AD8 is selected as input.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>AD9 is selected as input.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>AD10 is selected as input.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>AD11 is selected as input.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>AD12 is selected as input.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>AD13 is selected as input.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>AD14 is selected as input.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>AD15 is selected as input.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>AD18 is selected as input.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>AD19 is selected as input.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>AD21 is selected as input.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>AD22 is selected as input.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>AD23 is selected as input.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>ATX Sense</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>ATX Force</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>Temp Sensor</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>Band Gap</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>AD28 is selected as input.</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Module is disabled..</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion complete interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion complete interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COCO</name>
|
|
<description>Conversion Complete Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion is not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion is completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG1</name>
|
|
<description>ADC Configuration Register 1</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADICLK</name>
|
|
<description>Input Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Alternate clock 1 (ADC_ALTCLK1)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Alternate clock 2 (ADC_ALTCLK2)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Alternate clock 3 (ADC_ALTCLK3)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Alternate clock 4 (ADC_ALTCLK4)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Conversion mode selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>8-bit conversion.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>12-bit conversion.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>10-bit conversion.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADIV</name>
|
|
<description>Clock Divide Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The divide ratio is 1 and the clock rate is input clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG2</name>
|
|
<description>ADC Configuration Register 2</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMPLTS</name>
|
|
<description>Sample Time Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>R%s</name>
|
|
<description>ADC Data Result Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>Data result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1,2</dimIndex>
|
|
<name>CV%s</name>
|
|
<description>Compare Value Registers</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Compare Value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC2</name>
|
|
<description>Status and Control Register 2</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Voltage Reference Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default voltage reference pin pair, that is, external pins VREFH and VREFL</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACREN</name>
|
|
<description>Compare Function Range Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range function disabled. Only CV1 is compared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range function enabled. Both CV1 and CV2 are compared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFGT</name>
|
|
<description>Compare Function Greater Than Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFE</name>
|
|
<description>Compare Function Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRG</name>
|
|
<description>Conversion Trigger Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACT</name>
|
|
<description>Conversion Active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC3</name>
|
|
<description>Status and Control Register 3</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVGS</name>
|
|
<description>Hardware Average Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>4 samples averaged.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>8 samples averaged.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>16 samples averaged.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>32 samples averaged.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVGE</name>
|
|
<description>Hardware Average Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware average function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware average function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCO</name>
|
|
<description>Continuous Conversion Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>Calibration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_OFS</name>
|
|
<description>BASE Offset Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BA_OFS</name>
|
|
<description>Base Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFS</name>
|
|
<description>ADC Offset Correction Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USR_OFS</name>
|
|
<description>USER Offset Correction Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USR_OFS</name>
|
|
<description>USER Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XOFS</name>
|
|
<description>ADC X Offset Correction Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>YOFS</name>
|
|
<description>ADC Y Offset Correction Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x37</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YOFS</name>
|
|
<description>Y Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>G</name>
|
|
<description>ADC Gain Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2F0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>G</name>
|
|
<description>Gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UG</name>
|
|
<description>ADC User Gain Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>User Gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPS</name>
|
|
<description>ADC General Calibration Value Register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2E</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPS</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP3</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x180</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP3</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP2</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP2</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP1</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP1</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP0</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2E</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP0</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPX</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPX</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLPXEN</name>
|
|
<description>CLPX compare bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP9</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP9</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLP9EN</name>
|
|
<description>CLP9 compare bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPS_OFS</name>
|
|
<description>ADC General Calibration Value Register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPS_OFS</name>
|
|
<description>CLPS Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP3_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP3_OFS</name>
|
|
<description>CLP3 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP2_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP2_OFS</name>
|
|
<description>CLP2 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP1_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP1_OFS</name>
|
|
<description>CLP1 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP0_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP0_OFS</name>
|
|
<description>CLP0 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPX_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x440</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPX_OFS</name>
|
|
<description>CLPX Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP9_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x240</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP9_OFS</name>
|
|
<description>CLP9 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC1</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC1_</prependToName>
|
|
<baseAddress>0x40027000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xEC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC1</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>SC1%s</name>
|
|
<description>ADC Status and Control Registers 1</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADCH</name>
|
|
<description>Input channel select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>AD0 is selected as input.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>AD1 is selected as input.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>AD2 is selected as input.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>AD3 is selected as input.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>AD4 is selected as input.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>AD5 is selected as input.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>AD6 is selected as input.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>AD7 is selected as input.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>AD8 is selected as input.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>AD9 is selected as input.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>AD10 is selected as input.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>AD11 is selected as input.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>AD12 is selected as input.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>AD13 is selected as input.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>AD14 is selected as input.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>AD15 is selected as input.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>AD18 is selected as input.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>AD19 is selected as input.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>AD21 is selected as input.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>AD22 is selected as input.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>AD23 is selected as input.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>ATX Sense</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>ATX Force</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>Temp Sensor</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>Band Gap</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>AD28 is selected as input.</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>Module is disabled..</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion complete interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion complete interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COCO</name>
|
|
<description>Conversion Complete Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion is not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion is completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG1</name>
|
|
<description>ADC Configuration Register 1</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADICLK</name>
|
|
<description>Input Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Alternate clock 1 (ADC_ALTCLK1)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Alternate clock 2 (ADC_ALTCLK2)</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Alternate clock 3 (ADC_ALTCLK3)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Alternate clock 4 (ADC_ALTCLK4)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Conversion mode selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>8-bit conversion.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>12-bit conversion.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>10-bit conversion.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADIV</name>
|
|
<description>Clock Divide Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The divide ratio is 1 and the clock rate is input clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The divide ratio is 2 and the clock rate is (input clock)/2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The divide ratio is 4 and the clock rate is (input clock)/4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The divide ratio is 8 and the clock rate is (input clock)/8.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG2</name>
|
|
<description>ADC Configuration Register 2</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMPLTS</name>
|
|
<description>Sample Time Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>A,B</dimIndex>
|
|
<name>R%s</name>
|
|
<description>ADC Data Result Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>Data result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>1,2</dimIndex>
|
|
<name>CV%s</name>
|
|
<description>Compare Value Registers</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CV</name>
|
|
<description>Compare Value.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC2</name>
|
|
<description>Status and Control Register 2</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Voltage Reference Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Default voltage reference pin pair, that is, external pins VREFH and VREFL</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACREN</name>
|
|
<description>Compare Function Range Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Range function disabled. Only CV1 is compared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Range function enabled. Both CV1 and CV2 are compared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFGT</name>
|
|
<description>Compare Function Greater Than Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACFE</name>
|
|
<description>Compare Function Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compare function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compare function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADTRG</name>
|
|
<description>Conversion Trigger Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADACT</name>
|
|
<description>Conversion Active</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Conversion not in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Conversion in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC3</name>
|
|
<description>Status and Control Register 3</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVGS</name>
|
|
<description>Hardware Average Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>4 samples averaged.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>8 samples averaged.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>16 samples averaged.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>32 samples averaged.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVGE</name>
|
|
<description>Hardware Average Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware average function disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware average function enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADCO</name>
|
|
<description>Continuous Conversion Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>Calibration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE_OFS</name>
|
|
<description>BASE Offset Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x40</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BA_OFS</name>
|
|
<description>Base Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFS</name>
|
|
<description>ADC Offset Correction Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USR_OFS</name>
|
|
<description>USER Offset Correction Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>USR_OFS</name>
|
|
<description>USER Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XOFS</name>
|
|
<description>ADC X Offset Correction Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x30</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>OFS</name>
|
|
<description>Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>YOFS</name>
|
|
<description>ADC Y Offset Correction Register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x37</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>YOFS</name>
|
|
<description>Y Offset Error Correction Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>G</name>
|
|
<description>ADC Gain Register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2F0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>G</name>
|
|
<description>Gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UG</name>
|
|
<description>ADC User Gain Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>User Gain</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPS</name>
|
|
<description>ADC General Calibration Value Register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2E</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPS</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP3</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x180</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP3</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP2</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB8</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP2</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP1</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5C</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP1</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP0</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2E</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP0</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPX</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPX</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLPXEN</name>
|
|
<description>CLPX compare bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP9</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP9</name>
|
|
<description>Calibration Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLP9EN</name>
|
|
<description>CLP9 compare bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPS_OFS</name>
|
|
<description>ADC General Calibration Value Register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPS_OFS</name>
|
|
<description>CLPS Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP3_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP3_OFS</name>
|
|
<description>CLP3 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP2_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP2_OFS</name>
|
|
<description>CLP2 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP1_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP1_OFS</name>
|
|
<description>CLP1 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP0_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP0_OFS</name>
|
|
<description>CLP0 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLPX_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x440</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLPX_OFS</name>
|
|
<description>CLPX Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLP9_OFS</name>
|
|
<description>ADC Plus-Side General Calibration Value Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x240</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLP9_OFS</name>
|
|
<description>CLP9 Offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPSPI0</name>
|
|
<description>The LPSPI Memory Map/Register Definition can be found here.</description>
|
|
<groupName>LPSPI</groupName>
|
|
<prependToName>LPSPI0_</prependToName>
|
|
<baseAddress>0x4002C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x78</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPSPI0</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Module Identification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Standard feature set supporting 32-bit shift register.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>Module Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master logic is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master logic is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEN</name>
|
|
<description>Doze mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is disabled in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is enabled in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive Data is not ready.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is ready.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCF</name>
|
|
<description>Word Complete Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer word not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer word completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCF</name>
|
|
<description>Frame Complete Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame transfer has not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame transfer has completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All transfers have not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All transfers have completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEF</name>
|
|
<description>Transmit Error Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO underrun has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO underrun has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Receive Error Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMF</name>
|
|
<description>Data Match Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Have not received matching data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Have received matching data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBF</name>
|
|
<description>Module Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPSPI is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPSPI is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCIE</name>
|
|
<description>Word Complete Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCIE</name>
|
|
<description>Frame Complete Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer Complete Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transmit Error Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>Receive Error Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMIE</name>
|
|
<description>Data Match Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DER</name>
|
|
<description>DMA Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR0</name>
|
|
<description>Configuration Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HREN</name>
|
|
<description>Host Request Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRPOL</name>
|
|
<description>Host Request Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRSEL</name>
|
|
<description>Host Request Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host request input is pin LPSPI_HREQ.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host request input is input trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIRFIFO</name>
|
|
<description>Circular FIFO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Circular FIFO is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Circular FIFO is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMO</name>
|
|
<description>Receive Data Match Only</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is stored in the receive FIFO as normal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is discarded unless the DMF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR1</name>
|
|
<description>Configuration Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>Master Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Sample Point</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input data sampled on SCK edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Input data sampled on delayed SCK edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOPCS</name>
|
|
<description>Automatic PCS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Automatic PCS generation disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatic PCS generation enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOSTALL</name>
|
|
<description>No Stall</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfers will stall when transmit FIFO is empty or receive FIFO is full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSPOL</name>
|
|
<description>Peripheral Chip Select Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PCSx is active low.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PCSx is active high.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Match disabled.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Match enabled (1st data word equals MATCH0 OR MATCH1).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Match enabled (any data word equals MATCH0 OR MATCH1).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Match enabled (any data word equals MATCH0 AND next data word equals MATCH1)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Pin Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>SIN is used for input data and SOUT for output data.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>SIN is used for both input and output data.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>SOUT is used for both input and output data.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>SOUT is used for input data and SIN for output data.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTCFG</name>
|
|
<description>Output Config</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output data retains last value when chip select is negated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output data is tristated when chip select is negated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSCFG</name>
|
|
<description>Peripheral Chip Select Configuration</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PCS[3:2] are enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PCS[3:2] are disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMR0</name>
|
|
<description>Data Match Register 0</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH0</name>
|
|
<description>Match 0 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMR1</name>
|
|
<description>Data Match Register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH1</name>
|
|
<description>Match 1 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Clock Configuration Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCKDIV</name>
|
|
<description>SCK Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBT</name>
|
|
<description>Delay Between Transfers</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCSSCK</name>
|
|
<description>PCS to SCK Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCKPCS</name>
|
|
<description>SCK to PCS Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit FIFO Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive FIFO Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSR</name>
|
|
<description>FIFO Status Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit FIFO Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive FIFO Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Command Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAMESZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description>Transfer Width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Single bit transfer.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Two bit transfer.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Four bit transfer.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXMSK</name>
|
|
<description>Transmit Data Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Mask transmit data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXMSK</name>
|
|
<description>Receive Data Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is masked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONTC</name>
|
|
<description>Continuing Command</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command word for start of new transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command word for continuing transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Transfer</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Continuous transfer disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous transfer enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYSW</name>
|
|
<description>Byte Swap</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Byte swap disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Byte swap enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBF</name>
|
|
<description>LSB First</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is transferred MSB first.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is transferred LSB first.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Chip Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Transfer using LPSPI_PCS[0]</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Transfer using LPSPI_PCS[1]</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Transfer using LPSPI_PCS[2]</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Transfer using LPSPI_PCS[3]</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescaler Value</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state value of SCK is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state value of SCK is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSR</name>
|
|
<description>Receive Status Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Subsequent data word received after LPSPI_PCS assertion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>First data word received after LPSPI_PCS assertion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX FIFO Empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RX FIFO is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RX FIFO is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<description>Receive Data Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPSPI1</name>
|
|
<description>The LPSPI Memory Map/Register Definition can be found here.</description>
|
|
<groupName>LPSPI</groupName>
|
|
<prependToName>LPSPI1_</prependToName>
|
|
<baseAddress>0x4002D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x78</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPSPI1</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Module Identification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Standard feature set supporting 32-bit shift register.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>Module Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master logic is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master logic is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEN</name>
|
|
<description>Doze mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is disabled in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is enabled in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive Data is not ready.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is ready.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCF</name>
|
|
<description>Word Complete Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfer word not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfer word completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCF</name>
|
|
<description>Frame Complete Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Frame transfer has not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Frame transfer has completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer Complete Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All transfers have not completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All transfers have completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEF</name>
|
|
<description>Transmit Error Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO underrun has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO underrun has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REF</name>
|
|
<description>Receive Error Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMF</name>
|
|
<description>Data Match Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Have not received matching data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Have received matching data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBF</name>
|
|
<description>Module Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPSPI is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPSPI is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WCIE</name>
|
|
<description>Word Complete Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCIE</name>
|
|
<description>Frame Complete Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer Complete Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transmit Error Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>Receive Error Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMIE</name>
|
|
<description>Data Match Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DER</name>
|
|
<description>DMA Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR0</name>
|
|
<description>Configuration Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HREN</name>
|
|
<description>Host Request Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host request is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host request is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRPOL</name>
|
|
<description>Host Request Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRSEL</name>
|
|
<description>Host Request Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host request input is pin LPSPI_HREQ.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host request input is input trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIRFIFO</name>
|
|
<description>Circular FIFO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Circular FIFO is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Circular FIFO is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMO</name>
|
|
<description>Receive Data Match Only</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is stored in the receive FIFO as normal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is discarded unless the DMF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR1</name>
|
|
<description>Configuration Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>Master Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAMPLE</name>
|
|
<description>Sample Point</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Input data sampled on SCK edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Input data sampled on delayed SCK edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOPCS</name>
|
|
<description>Automatic PCS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Automatic PCS generation disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Automatic PCS generation enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOSTALL</name>
|
|
<description>No Stall</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transfers will stall when transmit FIFO is empty or receive FIFO is full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transfers will not stall, allowing transmit FIFO underrun or receive FIFO overrun to occur.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSPOL</name>
|
|
<description>Peripheral Chip Select Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PCSx is active low.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PCSx is active high.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Match disabled.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Match enabled (1st data word equals MATCH0 OR MATCH1).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Match enabled (any data word equals MATCH0 OR MATCH1).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Match enabled (any data word equals MATCH0 AND next data word equals MATCH1)</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1)</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Pin Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>SIN is used for input data and SOUT for output data.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>SIN is used for both input and output data.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>SOUT is used for both input and output data.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>SOUT is used for input data and SIN for output data.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTCFG</name>
|
|
<description>Output Config</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Output data retains last value when chip select is negated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Output data is tristated when chip select is negated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCSCFG</name>
|
|
<description>Peripheral Chip Select Configuration</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PCS[3:2] are enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PCS[3:2] are disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMR0</name>
|
|
<description>Data Match Register 0</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH0</name>
|
|
<description>Match 0 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMR1</name>
|
|
<description>Data Match Register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH1</name>
|
|
<description>Match 1 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>Clock Configuration Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SCKDIV</name>
|
|
<description>SCK Divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBT</name>
|
|
<description>Delay Between Transfers</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCSSCK</name>
|
|
<description>PCS to SCK Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCKPCS</name>
|
|
<description>SCK to PCS Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<description>FIFO Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit FIFO Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive FIFO Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSR</name>
|
|
<description>FIFO Status Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit FIFO Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive FIFO Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>Transmit Command Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1F</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRAMESZ</name>
|
|
<description>Frame Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description>Transfer Width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Single bit transfer.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Two bit transfer.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Four bit transfer.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXMSK</name>
|
|
<description>Transmit Data Mask</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Mask transmit data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXMSK</name>
|
|
<description>Receive Data Mask</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is masked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONTC</name>
|
|
<description>Continuing Command</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Command word for start of new transfer.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Command word for continuing transfer.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Transfer</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Continuous transfer disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Continuous transfer enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BYSW</name>
|
|
<description>Byte Swap</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Byte swap disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Byte swap enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LSBF</name>
|
|
<description>LSB First</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is transferred MSB first.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is transferred LSB first.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Chip Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Transfer using LPSPI_PCS[0]</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Transfer using LPSPI_PCS[1]</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Transfer using LPSPI_PCS[2]</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Transfer using LPSPI_PCS[3]</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescaler Value</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock Phase</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Data is captured on the leading edge of SCK and changed on the following edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Data is changed on the leading edge of SCK and captured on the following edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The inactive state value of SCK is low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The inactive state value of SCK is high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<description>Transmit Data Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSR</name>
|
|
<description>Receive Status Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Subsequent data word received after LPSPI_PCS assertion.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>First data word received after LPSPI_PCS assertion.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX FIFO Empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RX FIFO is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RX FIFO is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<description>Receive Data Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>Cyclic Redundancy Check</description>
|
|
<prependToName>CRC_</prependToName>
|
|
<baseAddress>0x40032000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>CRC Data register</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LL</name>
|
|
<description>CRC Low Lower Byte</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LU</name>
|
|
<description>CRC Low Upper Byte</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HL</name>
|
|
<description>CRC High Lower Byte</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HU</name>
|
|
<description>CRC High Upper Byte</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAL</name>
|
|
<description>CRC_DATAL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAL</name>
|
|
<description>DATAL stores the lower 16 bits of the 16/32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATALL</name>
|
|
<description>CRC_DATALL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATALL</name>
|
|
<description>CRCLL stores the first 8 bits of the 32 bit DATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATALU</name>
|
|
<description>CRC_DATALU register.</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATALU</name>
|
|
<description>DATALL stores the second 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAH</name>
|
|
<description>CRC_DATAH register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAH</name>
|
|
<description>DATAH stores the high 16 bits of the 16/32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAHL</name>
|
|
<description>CRC_DATAHL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHL</name>
|
|
<description>DATAHL stores the third 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATAHU</name>
|
|
<description>CRC_DATAHU register.</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHU</name>
|
|
<description>DATAHU stores the fourth 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLY</name>
|
|
<description>CRC Polynomial register</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1021</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOW</name>
|
|
<description>Low Polynominal Half-word</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HIGH</name>
|
|
<description>High Polynominal Half-word</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYL</name>
|
|
<description>CRC_GPOLYL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYL</name>
|
|
<description>POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYLL</name>
|
|
<description>CRC_GPOLYLL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYLL</name>
|
|
<description>POLYLL stores the first 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYLU</name>
|
|
<description>CRC_GPOLYLU register.</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYLU</name>
|
|
<description>POLYLL stores the second 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYH</name>
|
|
<description>CRC_GPOLYH register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>16</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYH</name>
|
|
<description>POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYHL</name>
|
|
<description>CRC_GPOLYHL register.</description>
|
|
<alternateGroup>CRC</alternateGroup>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYHL</name>
|
|
<description>POLYHL stores the third 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPOLYHU</name>
|
|
<description>CRC_GPOLYHU register.</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPOLYHU</name>
|
|
<description>POLYHU stores the fourth 8 bits of the 32 bit CRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>CRC Control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCRC</name>
|
|
<description>Width of CRC protocol.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>16-bit CRC protocol.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32-bit CRC protocol.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAS</name>
|
|
<description>Write CRC Data Register As Seed</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the CRC data register are data values.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the CRC data register are seed values.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FXOR</name>
|
|
<description>Complement Read Of CRC Data Register</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No XOR on reading.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invert or complement the read value of the CRC Data register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOTR</name>
|
|
<description>Type Of Transpose For Read</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed; bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOT</name>
|
|
<description>Type Of Transpose For Writes</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed; bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRLHU</name>
|
|
<description>CRC_CTRLHU register.</description>
|
|
<addressOffset>0xB</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCRC</name>
|
|
<description>no description available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>16-bit CRC protocol.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32-bit CRC protocol.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAS</name>
|
|
<description>no description available</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to CRC data register are data values.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to CRC data reguster are seed values.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FXOR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No XOR on reading.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Invert or complement the read value of CRC data register.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOTR</name>
|
|
<description>no description available</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No Transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed, bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOT</name>
|
|
<description>no description available</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No Transposition.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bits in bytes are transposed, bytes are not transposed.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Both bits in bytes and bytes are transposed.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Only bytes are transposed; no bits in a byte are transposed.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PDB0</name>
|
|
<description>Programmable Delay Block</description>
|
|
<prependToName>PDB0_</prependToName>
|
|
<baseAddress>0x40036000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x19C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PDB0</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status and Control register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load OK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous Mode Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB operation in One-Shot mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB operation in Continuous mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MULT</name>
|
|
<description>Multiplication Factor Select for Prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Multiplication factor is 1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Multiplication factor is 10.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Multiplication factor is 20.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Multiplication factor is 40.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDBIE</name>
|
|
<description>PDB Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDBIF</name>
|
|
<description>PDB Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PDBEN</name>
|
|
<description>PDB Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB disabled. Counter is off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Input Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Trigger-In 0 is selected.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Trigger-In 1 is selected.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Trigger-In 2 is selected.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Trigger-In 3 is selected.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Trigger-In 4 is selected.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Trigger-In 5 is selected.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Trigger-In 6 is selected.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Trigger-In 7 is selected.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Trigger-In 8 is selected.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Trigger-In 9 is selected.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Trigger-In 10 is selected.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Trigger-In 11 is selected.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Trigger-In 12 is selected.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Trigger-In 13 is selected.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Trigger-In 14 is selected.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Software trigger is selected.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Prescaler Divider Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Counting uses the peripheral clock divided by multiplication factor selected by MULT.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG</name>
|
|
<description>Software Trigger</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PDBEIE</name>
|
|
<description>PDB Sequence Error Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB sequence error interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB sequence error interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDMOD</name>
|
|
<description>Load Mode Select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulus register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>PDB Modulus</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>PDB Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDLY</name>
|
|
<description>Interrupt Delay register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>IDLY</name>
|
|
<description>PDB Interrupt Delay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x28</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CH%sC1</name>
|
|
<description>Channel n Control register 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>PDB Channel Pre-Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB channel's corresponding pre-trigger disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB channel's corresponding pre-trigger enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOS</name>
|
|
<description>PDB Channel Pre-Trigger Output Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BB</name>
|
|
<description>PDB Channel Pre-Trigger Back-to-Back Operation Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB channel's corresponding pre-trigger back-to-back operation disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB channel's corresponding pre-trigger back-to-back operation enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x28</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CH%sS</name>
|
|
<description>Channel n Status register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>PDB Channel Sequence Error Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sequence error not detected on PDB channel's corresponding pre-trigger.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CF</name>
|
|
<description>PDB Channel Flags</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x28</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CH%sDLY0</name>
|
|
<description>Channel n Delay 0 register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>PDB Channel Delay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x28</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>CH%sDLY1</name>
|
|
<description>Channel n Delay 1 register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY</name>
|
|
<description>PDB Channel Delay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POEN</name>
|
|
<description>Pulse-Out n Enable register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POEN</name>
|
|
<description>PDB Pulse-Out Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB Pulse-Out disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB Pulse-Out enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>PO%sDLY</name>
|
|
<description>Pulse-Out n Delay register</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DLY2</name>
|
|
<description>PDB Pulse-Out Delay 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DLY1</name>
|
|
<description>PDB Pulse-Out Delay 1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPIT0</name>
|
|
<description>Low Power Periodic Interrupt Timer (LPIT)</description>
|
|
<prependToName>LPIT0_</prependToName>
|
|
<baseAddress>0x40037000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x5C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPIT0</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x404</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CHANNEL</name>
|
|
<description>Number of Timer Channels</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EXT_TRIG</name>
|
|
<description>Number of External Trigger Inputs</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Module Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M_CEN</name>
|
|
<description>Module Clock Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Protocol clock to timers is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Protocol clock to timers is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW_RST</name>
|
|
<description>Software Reset Bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer channels and registers are not reset</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer channels and registers are reset</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZE_EN</name>
|
|
<description>DOZE Mode Enable Bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer channels are stopped in DOZE mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer channels continue to run in DOZE mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBG_EN</name>
|
|
<description>Debug Enable Bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer channels are stopped in Debug mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer channels continue to run in Debug mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Module Status Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIF0</name>
|
|
<description>Channel 0 Timer Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer has not timed out</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIF1</name>
|
|
<description>Channel 1 Timer Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer has not timed out</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIF2</name>
|
|
<description>Channel 2 Timer Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer has not timed out</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIF3</name>
|
|
<description>Channel 3 Timer Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer has not timed out</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timeout has occurred</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIER</name>
|
|
<description>Module Interrupt Enable Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIE0</name>
|
|
<description>Channel 0 Timer Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt generation is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt generation is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE1</name>
|
|
<description>Channel 1 Timer Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt generation is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt generation is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE2</name>
|
|
<description>Channel 2 Timer Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt generation is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt generation is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE3</name>
|
|
<description>Channel 3 Timer Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt generation is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt generation is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETTEN</name>
|
|
<description>Set Timer Enable Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SET_T_EN_0</name>
|
|
<description>Set Timer 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the Timer Channel 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_T_EN_1</name>
|
|
<description>Set Timer 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the Timer Channel 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_T_EN_2</name>
|
|
<description>Set Timer 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the Timer Channel 2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SET_T_EN_3</name>
|
|
<description>Set Timer 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the Timer Channel 3</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLRTEN</name>
|
|
<description>Clear Timer Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLR_T_EN_0</name>
|
|
<description>Clear Timer 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No action</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear T_EN bit for Timer Channel 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_T_EN_1</name>
|
|
<description>Clear Timer 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Action</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear T_EN bit for Timer Channel 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_T_EN_2</name>
|
|
<description>Clear Timer 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Action</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear T_EN bit for Timer Channel 2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLR_T_EN_3</name>
|
|
<description>Clear Timer 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No Action</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clear T_EN bit for Timer Channel 3</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TVAL%s</name>
|
|
<description>Timer Value Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMR_VAL</name>
|
|
<description>Timer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Invalid load value in compare modes</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>CVAL%s</name>
|
|
<description>Current Timer Value</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TMR_CUR_VAL</name>
|
|
<description>Current Timer Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TCTRL%s</name>
|
|
<description>Timer Control Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>T_EN</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer Channel is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer Channel is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHAIN</name>
|
|
<description>Chain Channel</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel Chaining is disabled. Channel Timer runs independently.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel Chaining is enabled. Timer decrements on previous channel's timeout</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Timer Operation Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>32-bit Periodic Counter</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Dual 16-bit Periodic Counter</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>32-bit Trigger Accumulator</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>32-bit Trigger Input Capture</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSOT</name>
|
|
<description>Timer Start On Trigger</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer starts to decrement immediately based on restart condition (controlled by TSOI bit)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer starts to decrement when rising edge on selected trigger is detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSOI</name>
|
|
<description>Timer Stop On Interrupt</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer does not stop after timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer will stop after timeout and will restart after rising edge on the T_EN bit is detected (i.e. timer channel is disabled and then enabled)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TROT</name>
|
|
<description>Timer Reload On Trigger</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer will not reload on selected trigger</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer will reload on selected trigger</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRG_SRC</name>
|
|
<description>Trigger Source</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger source selected in external</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger source selected is the internal trigger</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRG_SEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer channel 0 trigger source is selected</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer channel 1 trigger source is selected</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Timer channel 2 trigger source is selected</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM0</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM0_</prependToName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x224</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM0</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status And Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected. This in effect disables the FTM counter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-Aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in Up Counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in Up-Down Counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Reload Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reload interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reload interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RF</name>
|
|
<description>Reload Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter did not reach a reload point.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter reached a reload point.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>Channel 0 PWM enable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>Channel 1 PWM enable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>Channel 2 PWM enable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>Channel 3 PWM enable bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN4</name>
|
|
<description>Channel 4 PWM enable bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN5</name>
|
|
<description>Channel 5 PWM enable bit</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN6</name>
|
|
<description>Channel 6 PWM enable bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN7</name>
|
|
<description>Channel 7 PWM enable bit</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Modulo Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status And Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICRST</name>
|
|
<description>FTM counter reset by the selected input capture event.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter is not reset when the selected channel (n) input event is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is reset when the selected channel (n) input event is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Channel (n) Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Channel (n) Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel (n) Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel (n) Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel (n) Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel (n) interrupt. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel (n) interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel (n) Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel (n) event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel (n) event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGMODE</name>
|
|
<description>Trigger mode control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel outputs will generate the normal PWM outputs without generating a pulse.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHIS</name>
|
|
<description>Channel (n) Input State</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n) input is zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n) input is one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTIN</name>
|
|
<description>Counter Initial Value</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initial Value Of The FTM Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture And Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Features Mode Selection</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTMEN</name>
|
|
<description>FTM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TPM compatibility. Free running counter and synchronization compatible with TPM.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Free running counter and synchronization are different from TPM behavior.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialize The Channels Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPDIS</name>
|
|
<description>Write Protection Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSYNC</name>
|
|
<description>PWM Synchronization Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEST</name>
|
|
<description>Capture Test Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Capture test mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Capture test mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTM</name>
|
|
<description>Fault Control Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fault control is disabled for all channels.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIE</name>
|
|
<description>Fault Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault control interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault control interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>Synchronization</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMIN</name>
|
|
<description>Minimum Loading Point Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minimum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minimum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTMAX</name>
|
|
<description>Maximum Loading Point Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The maximum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The maximum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REINIT</name>
|
|
<description>FTM Counter Reinitialization By Synchronization (FTM counter synchronization)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter continues to count normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHOM</name>
|
|
<description>Output Mask Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0</name>
|
|
<description>PWM Synchronization Hardware Trigger 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1</name>
|
|
<description>PWM Synchronization Hardware Trigger 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2</name>
|
|
<description>PWM Synchronization Hardware Trigger 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSYNC</name>
|
|
<description>PWM Synchronization Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTINIT</name>
|
|
<description>Initial State For Channels Output</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OI</name>
|
|
<description>Channel 0 Output Initialization Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OI</name>
|
|
<description>Channel 1 Output Initialization Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OI</name>
|
|
<description>Channel 2 Output Initialization Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OI</name>
|
|
<description>Channel 3 Output Initialization Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OI</name>
|
|
<description>Channel 4 Output Initialization Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OI</name>
|
|
<description>Channel 5 Output Initialization Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OI</name>
|
|
<description>Channel 6 Output Initialization Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OI</name>
|
|
<description>Channel 7 Output Initialization Value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTMASK</name>
|
|
<description>Output Mask</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OM</name>
|
|
<description>Channel 0 Output Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OM</name>
|
|
<description>Channel 1 Output Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OM</name>
|
|
<description>Channel 2 Output Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OM</name>
|
|
<description>Channel 3 Output Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OM</name>
|
|
<description>Channel 4 Output Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OM</name>
|
|
<description>Channel 5 Output Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OM</name>
|
|
<description>Channel 6 Output Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OM</name>
|
|
<description>Channel 7 Output Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMBINE</name>
|
|
<description>Function For Linked Channels</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMBINE0</name>
|
|
<description>Combine Channels For n = 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Complement Of Channel (n) For n = 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN0</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP0</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN0</name>
|
|
<description>Deadtime Enable For n = 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN0</name>
|
|
<description>Synchronization Enable For n = 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN0</name>
|
|
<description>Fault Control Enable For n = 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE1</name>
|
|
<description>Combine Channels For n = 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Complement Of Channel (n) For n = 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN1</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP1</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN1</name>
|
|
<description>Deadtime Enable For n = 2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN1</name>
|
|
<description>Synchronization Enable For n = 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN1</name>
|
|
<description>Fault Control Enable For n = 2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE2</name>
|
|
<description>Combine Channels For n = 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2</name>
|
|
<description>Complement Of Channel (n) For n = 4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN2</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 4</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP2</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN2</name>
|
|
<description>Deadtime Enable For n = 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN2</name>
|
|
<description>Synchronization Enable For n = 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN2</name>
|
|
<description>Fault Control Enable For n = 4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE3</name>
|
|
<description>Combine Channels For n = 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3</name>
|
|
<description>Complement Of Channel (n) for n = 6</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN3</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP3</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN3</name>
|
|
<description>Deadtime Enable For n = 6</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN3</name>
|
|
<description>Synchronization Enable For n = 6</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN3</name>
|
|
<description>Fault Control Enable For n = 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEADTIME</name>
|
|
<description>Deadtime Insertion Control</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTVAL</name>
|
|
<description>Deadtime Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPS</name>
|
|
<description>Deadtime Prescaler Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x</name>
|
|
<description>Divide the system clock by 1.</description>
|
|
<value>#0x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divide the system clock by 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divide the system clock by 16.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTTRIG</name>
|
|
<description>FTM External Trigger</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH2TRIG</name>
|
|
<description>Channel 2 Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3TRIG</name>
|
|
<description>Channel 3 Trigger Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4TRIG</name>
|
|
<description>Channel 4 Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5TRIG</name>
|
|
<description>Channel 5 Trigger Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0TRIG</name>
|
|
<description>Channel 0 Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1TRIG</name>
|
|
<description>Channel 1 Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITTRIGEN</name>
|
|
<description>Initialization Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of initialization trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of initialization trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGF</name>
|
|
<description>Channel Trigger Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel trigger was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel trigger was generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6TRIG</name>
|
|
<description>Channel 6 Trigger Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7TRIG</name>
|
|
<description>Channel 7 Trigger Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Channels Polarity</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Channel 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Channel 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Channel 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Channel 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Channel 4 Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Channel 5 Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL6</name>
|
|
<description>Channel 6 Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL7</name>
|
|
<description>Channel 7 Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMS</name>
|
|
<description>Fault Mode Status</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULTF0</name>
|
|
<description>Fault Detection Flag 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF1</name>
|
|
<description>Fault Detection Flag 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF2</name>
|
|
<description>Fault Detection Flag 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF3</name>
|
|
<description>Fault Detection Flag 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIN</name>
|
|
<description>Fault Inputs</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The logic OR of the enabled fault inputs is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The logic OR of the enabled fault inputs is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is disabled. Write protected bits can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is enabled. Write protected bits cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF</name>
|
|
<description>Fault Detection Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER</name>
|
|
<description>Input Capture Filter Control</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0FVAL</name>
|
|
<description>Channel 0 Input Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1FVAL</name>
|
|
<description>Channel 1 Input Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2FVAL</name>
|
|
<description>Channel 2 Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3FVAL</name>
|
|
<description>Channel 3 Input Filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCTRL</name>
|
|
<description>Fault Control</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULT0EN</name>
|
|
<description>Fault Input 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1EN</name>
|
|
<description>Fault Input 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2EN</name>
|
|
<description>Fault Input 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT3EN</name>
|
|
<description>Fault Input 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR0EN</name>
|
|
<description>Fault Input 0 Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR1EN</name>
|
|
<description>Fault Input 1 Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR2EN</name>
|
|
<description>Fault Input 2 Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR3EN</name>
|
|
<description>Fault Input 3 Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFVAL</name>
|
|
<description>Fault Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTATE</name>
|
|
<description>Fault output state</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM outputs will be tri-stated when fault event is ongoing</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QDCTRL</name>
|
|
<description>Quadrature Decoder Control And Status</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>QUADEN</name>
|
|
<description>Quadrature Decoder Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Quadrature Decoder mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Quadrature Decoder mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOFDIR</name>
|
|
<description>Timer Overflow Direction In Quadrature Decoder Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADIR</name>
|
|
<description>FTM Counter Direction In Quadrature Decoder Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Counting direction is decreasing (FTM counter decrement).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counting direction is increasing (FTM counter increment).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADMODE</name>
|
|
<description>Quadrature Decoder Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A and phase B encoding mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count and direction encoding mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBPOL</name>
|
|
<description>Phase B Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAPOL</name>
|
|
<description>Phase A Input Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBFLTREN</name>
|
|
<description>Phase B Input Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase B input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase B input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAFLTREN</name>
|
|
<description>Phase A Input Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase A input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LDFQ</name>
|
|
<description>Load Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BDMMODE</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global Time Base Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Use of an external global time base is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use of an external global time base is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEOUT</name>
|
|
<description>Global Time Base Output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A global time base signal generation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A global time base signal generation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITRIGR</name>
|
|
<description>Initialization trigger on Reload Point</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Initialization trigger is generated on counter wrap events.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initialization trigger is generated when a reload point is reached.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTPOL</name>
|
|
<description>FTM Fault Input Polarity</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT0POL</name>
|
|
<description>Fault Input 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT1POL</name>
|
|
<description>Fault Input 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT2POL</name>
|
|
<description>Fault Input 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT3POL</name>
|
|
<description>Fault Input 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCONF</name>
|
|
<description>Synchronization Configuration</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWTRIGMODE</name>
|
|
<description>Hardware Trigger Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTINC</name>
|
|
<description>CNTIN Register Synchronization</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVC</name>
|
|
<description>INVCTRL Register Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOC</name>
|
|
<description>SWOCTRL Register Synchronization</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMODE</name>
|
|
<description>Synchronization Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Legacy PWM synchronization is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enhanced PWM synchronization is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTCNT</name>
|
|
<description>FTM counter synchronization is activated by the software trigger.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWWRBUF</name>
|
|
<description>MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOM</name>
|
|
<description>Output mask synchronization is activated by the software trigger.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWINVC</name>
|
|
<description>Inverting control synchronization is activated by the software trigger.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSOC</name>
|
|
<description>Software output control synchronization is activated by the software trigger.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWRSTCNT</name>
|
|
<description>FTM counter synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWWRBUF</name>
|
|
<description>MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWOM</name>
|
|
<description>Output mask synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWINVC</name>
|
|
<description>Inverting control synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWSOC</name>
|
|
<description>Software output control synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVCTRL</name>
|
|
<description>FTM Inverting Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV0EN</name>
|
|
<description>Pair Channels 0 Inverting Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV1EN</name>
|
|
<description>Pair Channels 1 Inverting Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV2EN</name>
|
|
<description>Pair Channels 2 Inverting Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV3EN</name>
|
|
<description>Pair Channels 3 Inverting Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWOCTRL</name>
|
|
<description>FTM Software Output Control</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OC</name>
|
|
<description>Channel 0 Software Output Control Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OC</name>
|
|
<description>Channel 1 Software Output Control Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OC</name>
|
|
<description>Channel 2 Software Output Control Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OC</name>
|
|
<description>Channel 3 Software Output Control Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OC</name>
|
|
<description>Channel 4 Software Output Control Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OC</name>
|
|
<description>Channel 5 Software Output Control Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OC</name>
|
|
<description>Channel 6 Software Output Control Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OC</name>
|
|
<description>Channel 7 Software Output Control Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0OCV</name>
|
|
<description>Channel 0 Software Output Control Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OCV</name>
|
|
<description>Channel 1 Software Output Control Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OCV</name>
|
|
<description>Channel 2 Software Output Control Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OCV</name>
|
|
<description>Channel 3 Software Output Control Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OCV</name>
|
|
<description>Channel 4 Software Output Control Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OCV</name>
|
|
<description>Channel 5 Software Output Control Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OCV</name>
|
|
<description>Channel 6 Software Output Control Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OCV</name>
|
|
<description>Channel 7 Software Output Control Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMLOAD</name>
|
|
<description>FTM PWM Load</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SEL</name>
|
|
<description>Channel 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1SEL</name>
|
|
<description>Channel 1 Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2SEL</name>
|
|
<description>Channel 2 Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3SEL</name>
|
|
<description>Channel 3 Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4SEL</name>
|
|
<description>Channel 4 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5SEL</name>
|
|
<description>Channel 5 Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6SEL</name>
|
|
<description>Channel 6 Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7SEL</name>
|
|
<description>Channel 7 Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCSEL</name>
|
|
<description>Half Cycle Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Half cycle reload is disabled and it is not considered as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Half cycle reload is enabled and it is considered as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loading updated values is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loading updated values is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GLEN</name>
|
|
<description>Global Load Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Global Load Ok disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GLDOK</name>
|
|
<description>Global Load OK</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No action.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LDOK bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCR</name>
|
|
<description>Half Cycle Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HCVAL</name>
|
|
<description>Half Cycle Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD_MIRROR</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACMOD</name>
|
|
<description>Fractional Value for MOD register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Modulo Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>C%sV_MIRROR</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL</name>
|
|
<description>Fractional Value for VAL register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM1</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM1_</prependToName>
|
|
<baseAddress>0x40039000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x224</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM1</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status And Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected. This in effect disables the FTM counter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-Aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in Up Counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in Up-Down Counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Reload Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reload interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reload interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RF</name>
|
|
<description>Reload Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter did not reach a reload point.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter reached a reload point.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>Channel 0 PWM enable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>Channel 1 PWM enable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>Channel 2 PWM enable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>Channel 3 PWM enable bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN4</name>
|
|
<description>Channel 4 PWM enable bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN5</name>
|
|
<description>Channel 5 PWM enable bit</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN6</name>
|
|
<description>Channel 6 PWM enable bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN7</name>
|
|
<description>Channel 7 PWM enable bit</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Modulo Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status And Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICRST</name>
|
|
<description>FTM counter reset by the selected input capture event.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter is not reset when the selected channel (n) input event is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is reset when the selected channel (n) input event is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Channel (n) Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Channel (n) Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel (n) Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel (n) Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel (n) Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel (n) interrupt. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel (n) interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel (n) Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel (n) event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel (n) event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGMODE</name>
|
|
<description>Trigger mode control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel outputs will generate the normal PWM outputs without generating a pulse.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHIS</name>
|
|
<description>Channel (n) Input State</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n) input is zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n) input is one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTIN</name>
|
|
<description>Counter Initial Value</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initial Value Of The FTM Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture And Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Features Mode Selection</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTMEN</name>
|
|
<description>FTM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TPM compatibility. Free running counter and synchronization compatible with TPM.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Free running counter and synchronization are different from TPM behavior.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialize The Channels Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPDIS</name>
|
|
<description>Write Protection Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSYNC</name>
|
|
<description>PWM Synchronization Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEST</name>
|
|
<description>Capture Test Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Capture test mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Capture test mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTM</name>
|
|
<description>Fault Control Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fault control is disabled for all channels.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIE</name>
|
|
<description>Fault Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault control interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault control interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>Synchronization</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMIN</name>
|
|
<description>Minimum Loading Point Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minimum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minimum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTMAX</name>
|
|
<description>Maximum Loading Point Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The maximum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The maximum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REINIT</name>
|
|
<description>FTM Counter Reinitialization By Synchronization (FTM counter synchronization)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter continues to count normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHOM</name>
|
|
<description>Output Mask Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0</name>
|
|
<description>PWM Synchronization Hardware Trigger 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1</name>
|
|
<description>PWM Synchronization Hardware Trigger 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2</name>
|
|
<description>PWM Synchronization Hardware Trigger 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSYNC</name>
|
|
<description>PWM Synchronization Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTINIT</name>
|
|
<description>Initial State For Channels Output</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OI</name>
|
|
<description>Channel 0 Output Initialization Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OI</name>
|
|
<description>Channel 1 Output Initialization Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OI</name>
|
|
<description>Channel 2 Output Initialization Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OI</name>
|
|
<description>Channel 3 Output Initialization Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OI</name>
|
|
<description>Channel 4 Output Initialization Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OI</name>
|
|
<description>Channel 5 Output Initialization Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OI</name>
|
|
<description>Channel 6 Output Initialization Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OI</name>
|
|
<description>Channel 7 Output Initialization Value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTMASK</name>
|
|
<description>Output Mask</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OM</name>
|
|
<description>Channel 0 Output Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OM</name>
|
|
<description>Channel 1 Output Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OM</name>
|
|
<description>Channel 2 Output Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OM</name>
|
|
<description>Channel 3 Output Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OM</name>
|
|
<description>Channel 4 Output Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OM</name>
|
|
<description>Channel 5 Output Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OM</name>
|
|
<description>Channel 6 Output Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OM</name>
|
|
<description>Channel 7 Output Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMBINE</name>
|
|
<description>Function For Linked Channels</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMBINE0</name>
|
|
<description>Combine Channels For n = 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Complement Of Channel (n) For n = 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN0</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP0</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN0</name>
|
|
<description>Deadtime Enable For n = 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN0</name>
|
|
<description>Synchronization Enable For n = 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN0</name>
|
|
<description>Fault Control Enable For n = 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE1</name>
|
|
<description>Combine Channels For n = 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Complement Of Channel (n) For n = 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN1</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP1</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN1</name>
|
|
<description>Deadtime Enable For n = 2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN1</name>
|
|
<description>Synchronization Enable For n = 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN1</name>
|
|
<description>Fault Control Enable For n = 2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE2</name>
|
|
<description>Combine Channels For n = 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2</name>
|
|
<description>Complement Of Channel (n) For n = 4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN2</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 4</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP2</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN2</name>
|
|
<description>Deadtime Enable For n = 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN2</name>
|
|
<description>Synchronization Enable For n = 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN2</name>
|
|
<description>Fault Control Enable For n = 4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE3</name>
|
|
<description>Combine Channels For n = 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3</name>
|
|
<description>Complement Of Channel (n) for n = 6</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN3</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP3</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN3</name>
|
|
<description>Deadtime Enable For n = 6</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN3</name>
|
|
<description>Synchronization Enable For n = 6</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN3</name>
|
|
<description>Fault Control Enable For n = 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEADTIME</name>
|
|
<description>Deadtime Insertion Control</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTVAL</name>
|
|
<description>Deadtime Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPS</name>
|
|
<description>Deadtime Prescaler Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x</name>
|
|
<description>Divide the system clock by 1.</description>
|
|
<value>#0x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divide the system clock by 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divide the system clock by 16.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTTRIG</name>
|
|
<description>FTM External Trigger</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH2TRIG</name>
|
|
<description>Channel 2 Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3TRIG</name>
|
|
<description>Channel 3 Trigger Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4TRIG</name>
|
|
<description>Channel 4 Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5TRIG</name>
|
|
<description>Channel 5 Trigger Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0TRIG</name>
|
|
<description>Channel 0 Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1TRIG</name>
|
|
<description>Channel 1 Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITTRIGEN</name>
|
|
<description>Initialization Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of initialization trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of initialization trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGF</name>
|
|
<description>Channel Trigger Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel trigger was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel trigger was generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6TRIG</name>
|
|
<description>Channel 6 Trigger Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7TRIG</name>
|
|
<description>Channel 7 Trigger Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Channels Polarity</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Channel 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Channel 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Channel 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Channel 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Channel 4 Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Channel 5 Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL6</name>
|
|
<description>Channel 6 Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL7</name>
|
|
<description>Channel 7 Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMS</name>
|
|
<description>Fault Mode Status</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULTF0</name>
|
|
<description>Fault Detection Flag 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF1</name>
|
|
<description>Fault Detection Flag 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF2</name>
|
|
<description>Fault Detection Flag 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF3</name>
|
|
<description>Fault Detection Flag 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIN</name>
|
|
<description>Fault Inputs</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The logic OR of the enabled fault inputs is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The logic OR of the enabled fault inputs is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is disabled. Write protected bits can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is enabled. Write protected bits cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF</name>
|
|
<description>Fault Detection Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER</name>
|
|
<description>Input Capture Filter Control</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0FVAL</name>
|
|
<description>Channel 0 Input Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1FVAL</name>
|
|
<description>Channel 1 Input Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2FVAL</name>
|
|
<description>Channel 2 Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3FVAL</name>
|
|
<description>Channel 3 Input Filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCTRL</name>
|
|
<description>Fault Control</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULT0EN</name>
|
|
<description>Fault Input 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1EN</name>
|
|
<description>Fault Input 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2EN</name>
|
|
<description>Fault Input 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT3EN</name>
|
|
<description>Fault Input 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR0EN</name>
|
|
<description>Fault Input 0 Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR1EN</name>
|
|
<description>Fault Input 1 Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR2EN</name>
|
|
<description>Fault Input 2 Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR3EN</name>
|
|
<description>Fault Input 3 Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFVAL</name>
|
|
<description>Fault Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTATE</name>
|
|
<description>Fault output state</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM outputs will be tri-stated when fault event is ongoing</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QDCTRL</name>
|
|
<description>Quadrature Decoder Control And Status</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>QUADEN</name>
|
|
<description>Quadrature Decoder Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Quadrature Decoder mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Quadrature Decoder mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOFDIR</name>
|
|
<description>Timer Overflow Direction In Quadrature Decoder Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADIR</name>
|
|
<description>FTM Counter Direction In Quadrature Decoder Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Counting direction is decreasing (FTM counter decrement).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counting direction is increasing (FTM counter increment).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADMODE</name>
|
|
<description>Quadrature Decoder Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A and phase B encoding mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count and direction encoding mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBPOL</name>
|
|
<description>Phase B Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAPOL</name>
|
|
<description>Phase A Input Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBFLTREN</name>
|
|
<description>Phase B Input Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase B input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase B input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAFLTREN</name>
|
|
<description>Phase A Input Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase A input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LDFQ</name>
|
|
<description>Load Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BDMMODE</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global Time Base Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Use of an external global time base is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use of an external global time base is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEOUT</name>
|
|
<description>Global Time Base Output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A global time base signal generation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A global time base signal generation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITRIGR</name>
|
|
<description>Initialization trigger on Reload Point</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Initialization trigger is generated on counter wrap events.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initialization trigger is generated when a reload point is reached.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTPOL</name>
|
|
<description>FTM Fault Input Polarity</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT0POL</name>
|
|
<description>Fault Input 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT1POL</name>
|
|
<description>Fault Input 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT2POL</name>
|
|
<description>Fault Input 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT3POL</name>
|
|
<description>Fault Input 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCONF</name>
|
|
<description>Synchronization Configuration</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWTRIGMODE</name>
|
|
<description>Hardware Trigger Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTINC</name>
|
|
<description>CNTIN Register Synchronization</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVC</name>
|
|
<description>INVCTRL Register Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOC</name>
|
|
<description>SWOCTRL Register Synchronization</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMODE</name>
|
|
<description>Synchronization Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Legacy PWM synchronization is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enhanced PWM synchronization is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTCNT</name>
|
|
<description>FTM counter synchronization is activated by the software trigger.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWWRBUF</name>
|
|
<description>MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOM</name>
|
|
<description>Output mask synchronization is activated by the software trigger.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWINVC</name>
|
|
<description>Inverting control synchronization is activated by the software trigger.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSOC</name>
|
|
<description>Software output control synchronization is activated by the software trigger.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWRSTCNT</name>
|
|
<description>FTM counter synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWWRBUF</name>
|
|
<description>MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWOM</name>
|
|
<description>Output mask synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWINVC</name>
|
|
<description>Inverting control synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWSOC</name>
|
|
<description>Software output control synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVCTRL</name>
|
|
<description>FTM Inverting Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV0EN</name>
|
|
<description>Pair Channels 0 Inverting Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV1EN</name>
|
|
<description>Pair Channels 1 Inverting Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV2EN</name>
|
|
<description>Pair Channels 2 Inverting Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV3EN</name>
|
|
<description>Pair Channels 3 Inverting Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWOCTRL</name>
|
|
<description>FTM Software Output Control</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OC</name>
|
|
<description>Channel 0 Software Output Control Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OC</name>
|
|
<description>Channel 1 Software Output Control Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OC</name>
|
|
<description>Channel 2 Software Output Control Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OC</name>
|
|
<description>Channel 3 Software Output Control Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OC</name>
|
|
<description>Channel 4 Software Output Control Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OC</name>
|
|
<description>Channel 5 Software Output Control Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OC</name>
|
|
<description>Channel 6 Software Output Control Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OC</name>
|
|
<description>Channel 7 Software Output Control Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0OCV</name>
|
|
<description>Channel 0 Software Output Control Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OCV</name>
|
|
<description>Channel 1 Software Output Control Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OCV</name>
|
|
<description>Channel 2 Software Output Control Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OCV</name>
|
|
<description>Channel 3 Software Output Control Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OCV</name>
|
|
<description>Channel 4 Software Output Control Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OCV</name>
|
|
<description>Channel 5 Software Output Control Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OCV</name>
|
|
<description>Channel 6 Software Output Control Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OCV</name>
|
|
<description>Channel 7 Software Output Control Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMLOAD</name>
|
|
<description>FTM PWM Load</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SEL</name>
|
|
<description>Channel 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1SEL</name>
|
|
<description>Channel 1 Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2SEL</name>
|
|
<description>Channel 2 Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3SEL</name>
|
|
<description>Channel 3 Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4SEL</name>
|
|
<description>Channel 4 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5SEL</name>
|
|
<description>Channel 5 Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6SEL</name>
|
|
<description>Channel 6 Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7SEL</name>
|
|
<description>Channel 7 Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCSEL</name>
|
|
<description>Half Cycle Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Half cycle reload is disabled and it is not considered as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Half cycle reload is enabled and it is considered as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loading updated values is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loading updated values is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GLEN</name>
|
|
<description>Global Load Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Global Load Ok disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GLDOK</name>
|
|
<description>Global Load OK</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No action.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LDOK bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCR</name>
|
|
<description>Half Cycle Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HCVAL</name>
|
|
<description>Half Cycle Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD_MIRROR</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACMOD</name>
|
|
<description>Fractional Value for MOD register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Modulo Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>C%sV_MIRROR</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL</name>
|
|
<description>Fractional Value for VAL register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FTM2</name>
|
|
<description>FlexTimer Module</description>
|
|
<groupName>FTM</groupName>
|
|
<prependToName>FTM2_</prependToName>
|
|
<baseAddress>0x4003A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x224</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FTM2</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SC</name>
|
|
<description>Status And Control</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Prescale Factor Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKS</name>
|
|
<description>Clock Source Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No clock selected. This in effect disables the FTM counter.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>System clock</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fixed frequency clock</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>External clock</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPWMS</name>
|
|
<description>Center-Aligned PWM Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter operates in Up Counting mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter operates in Up-Down Counting mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Reload Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reload interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reload interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RF</name>
|
|
<description>Reload Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter did not reach a reload point.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter reached a reload point.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Timer Overflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable TOF interrupts. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable TOF interrupts. An interrupt is generated when TOF equals one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timer Overflow Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter has not overflowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter has overflowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN0</name>
|
|
<description>Channel 0 PWM enable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN1</name>
|
|
<description>Channel 1 PWM enable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN2</name>
|
|
<description>Channel 2 PWM enable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN3</name>
|
|
<description>Channel 3 PWM enable bit</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN4</name>
|
|
<description>Channel 4 PWM enable bit</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN5</name>
|
|
<description>Channel 5 PWM enable bit</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN6</name>
|
|
<description>Channel 6 PWM enable bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMEN7</name>
|
|
<description>Channel 7 PWM enable bit</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output port is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output port is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Counter</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Modulo Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>C%sSC</name>
|
|
<description>Channel (n) Status And Control</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMA</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable DMA transfers.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable DMA transfers.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ICRST</name>
|
|
<description>FTM counter reset by the selected input capture event.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter is not reset when the selected channel (n) input event is detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is reset when the selected channel (n) input event is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELSA</name>
|
|
<description>Channel (n) Edge or Level Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ELSB</name>
|
|
<description>Channel (n) Edge or Level Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSA</name>
|
|
<description>Channel (n) Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSB</name>
|
|
<description>Channel (n) Mode Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel (n) Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable channel (n) interrupt. Use software polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable channel (n) interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHF</name>
|
|
<description>Channel (n) Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel (n) event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel (n) event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGMODE</name>
|
|
<description>Trigger mode control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel outputs will generate the normal PWM outputs without generating a pulse.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHIS</name>
|
|
<description>Channel (n) Input State</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n) input is zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n) input is one.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x8</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>C%sV</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTIN</name>
|
|
<description>Counter Initial Value</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initial Value Of The FTM Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>Capture And Compare Status</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel event has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel event has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>Features Mode Selection</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTMEN</name>
|
|
<description>FTM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TPM compatibility. Free running counter and synchronization compatible with TPM.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Free running counter and synchronization are different from TPM behavior.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialize The Channels Output</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPDIS</name>
|
|
<description>Write Protection Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWMSYNC</name>
|
|
<description>PWM Synchronization Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CAPTEST</name>
|
|
<description>Capture Test Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Capture test mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Capture test mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTM</name>
|
|
<description>Fault Control Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fault control is disabled for all channels.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the manual fault clearing.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIE</name>
|
|
<description>Fault Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault control interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault control interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>Synchronization</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTMIN</name>
|
|
<description>Minimum Loading Point Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The minimum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The minimum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTMAX</name>
|
|
<description>Maximum Loading Point Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The maximum loading point is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The maximum loading point is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REINIT</name>
|
|
<description>FTM Counter Reinitialization By Synchronization (FTM counter synchronization)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM counter continues to count normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM counter is updated with its initial value when the selected trigger is detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCHOM</name>
|
|
<description>Output Mask Synchronization</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OUTMASK register is updated with the value of its buffer only by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG0</name>
|
|
<description>PWM Synchronization Hardware Trigger 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG1</name>
|
|
<description>PWM Synchronization Hardware Trigger 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIG2</name>
|
|
<description>PWM Synchronization Hardware Trigger 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSYNC</name>
|
|
<description>PWM Synchronization Software Trigger</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software trigger is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTINIT</name>
|
|
<description>Initial State For Channels Output</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OI</name>
|
|
<description>Channel 0 Output Initialization Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OI</name>
|
|
<description>Channel 1 Output Initialization Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OI</name>
|
|
<description>Channel 2 Output Initialization Value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OI</name>
|
|
<description>Channel 3 Output Initialization Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OI</name>
|
|
<description>Channel 4 Output Initialization Value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OI</name>
|
|
<description>Channel 5 Output Initialization Value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OI</name>
|
|
<description>Channel 6 Output Initialization Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OI</name>
|
|
<description>Channel 7 Output Initialization Value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The initialization value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The initialization value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTMASK</name>
|
|
<description>Output Mask</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OM</name>
|
|
<description>Channel 0 Output Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OM</name>
|
|
<description>Channel 1 Output Mask</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OM</name>
|
|
<description>Channel 2 Output Mask</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OM</name>
|
|
<description>Channel 3 Output Mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OM</name>
|
|
<description>Channel 4 Output Mask</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OM</name>
|
|
<description>Channel 5 Output Mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OM</name>
|
|
<description>Channel 6 Output Mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OM</name>
|
|
<description>Channel 7 Output Mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel output is not masked. It continues to operate normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel output is masked. It is forced to its inactive state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMBINE</name>
|
|
<description>Function For Linked Channels</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMBINE0</name>
|
|
<description>Combine Channels For n = 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP0</name>
|
|
<description>Complement Of Channel (n) For n = 0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN0</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP0</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN0</name>
|
|
<description>Deadtime Enable For n = 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN0</name>
|
|
<description>Synchronization Enable For n = 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN0</name>
|
|
<description>Fault Control Enable For n = 0</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE1</name>
|
|
<description>Combine Channels For n = 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1</name>
|
|
<description>Complement Of Channel (n) For n = 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN1</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP1</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN1</name>
|
|
<description>Deadtime Enable For n = 2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN1</name>
|
|
<description>Synchronization Enable For n = 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN1</name>
|
|
<description>Fault Control Enable For n = 2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE2</name>
|
|
<description>Combine Channels For n = 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2</name>
|
|
<description>Complement Of Channel (n) For n = 4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN2</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 4</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP2</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 4</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN2</name>
|
|
<description>Deadtime Enable For n = 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN2</name>
|
|
<description>Synchronization Enable For n = 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN2</name>
|
|
<description>Fault Control Enable For n = 4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMBINE3</name>
|
|
<description>Combine Channels For n = 6</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3</name>
|
|
<description>Complement Of Channel (n) for n = 6</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel (n+1) output is the same as the channel (n) output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel (n+1) output is the complement of the channel (n) output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECAPEN3</name>
|
|
<description>Dual Edge Capture Mode Enable For n = 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DECAP3</name>
|
|
<description>Dual Edge Capture Mode Captures For n = 6</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dual edge captures are inactive.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dual edge captures are active.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DTEN3</name>
|
|
<description>Deadtime Enable For n = 6</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The deadtime insertion in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The deadtime insertion in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN3</name>
|
|
<description>Synchronization Enable For n = 6</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWM synchronization in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWM synchronization in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTEN3</name>
|
|
<description>Fault Control Enable For n = 6</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault control in this pair of channels is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault control in this pair of channels is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEADTIME</name>
|
|
<description>Deadtime Insertion Control</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTVAL</name>
|
|
<description>Deadtime Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTPS</name>
|
|
<description>Deadtime Prescaler Value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x</name>
|
|
<description>Divide the system clock by 1.</description>
|
|
<value>#0x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divide the system clock by 4.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divide the system clock by 16.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTTRIG</name>
|
|
<description>FTM External Trigger</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH2TRIG</name>
|
|
<description>Channel 2 Trigger Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3TRIG</name>
|
|
<description>Channel 3 Trigger Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4TRIG</name>
|
|
<description>Channel 4 Trigger Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5TRIG</name>
|
|
<description>Channel 5 Trigger Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0TRIG</name>
|
|
<description>Channel 0 Trigger Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1TRIG</name>
|
|
<description>Channel 1 Trigger Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INITTRIGEN</name>
|
|
<description>Initialization Trigger Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of initialization trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of initialization trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIGF</name>
|
|
<description>Channel Trigger Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No channel trigger was generated.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A channel trigger was generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6TRIG</name>
|
|
<description>Channel 6 Trigger Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7TRIG</name>
|
|
<description>Channel 7 Trigger Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The generation of the channel trigger is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The generation of the channel trigger is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POL</name>
|
|
<description>Channels Polarity</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>POL0</name>
|
|
<description>Channel 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Channel 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Channel 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL3</name>
|
|
<description>Channel 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL4</name>
|
|
<description>Channel 4 Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL5</name>
|
|
<description>Channel 5 Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL6</name>
|
|
<description>Channel 6 Polarity</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POL7</name>
|
|
<description>Channel 7 Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel polarity is active high.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel polarity is active low.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMS</name>
|
|
<description>Fault Mode Status</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULTF0</name>
|
|
<description>Fault Detection Flag 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF1</name>
|
|
<description>Fault Detection Flag 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF2</name>
|
|
<description>Fault Detection Flag 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF3</name>
|
|
<description>Fault Detection Flag 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected at the fault input.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected at the fault input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTIN</name>
|
|
<description>Fault Inputs</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The logic OR of the enabled fault inputs is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The logic OR of the enabled fault inputs is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write Protection Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Write protection is disabled. Write protected bits can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write protection is enabled. Write protected bits cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULTF</name>
|
|
<description>Fault Detection Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No fault condition was detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A fault condition was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FILTER</name>
|
|
<description>Input Capture Filter Control</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0FVAL</name>
|
|
<description>Channel 0 Input Filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1FVAL</name>
|
|
<description>Channel 1 Input Filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2FVAL</name>
|
|
<description>Channel 2 Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3FVAL</name>
|
|
<description>Channel 3 Input Filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCTRL</name>
|
|
<description>Fault Control</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FAULT0EN</name>
|
|
<description>Fault Input 0 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1EN</name>
|
|
<description>Fault Input 1 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2EN</name>
|
|
<description>Fault Input 2 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FAULT3EN</name>
|
|
<description>Fault Input 3 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR0EN</name>
|
|
<description>Fault Input 0 Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR1EN</name>
|
|
<description>Fault Input 1 Filter Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR2EN</name>
|
|
<description>Fault Input 2 Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFLTR3EN</name>
|
|
<description>Fault Input 3 Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fault input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fault input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FFVAL</name>
|
|
<description>Fault Input Filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTATE</name>
|
|
<description>Fault output state</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM outputs will be tri-stated when fault event is ongoing</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QDCTRL</name>
|
|
<description>Quadrature Decoder Control And Status</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>QUADEN</name>
|
|
<description>Quadrature Decoder Mode Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Quadrature Decoder mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Quadrature Decoder mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOFDIR</name>
|
|
<description>Timer Overflow Direction In Quadrature Decoder Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADIR</name>
|
|
<description>FTM Counter Direction In Quadrature Decoder Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Counting direction is decreasing (FTM counter decrement).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Counting direction is increasing (FTM counter increment).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>QUADMODE</name>
|
|
<description>Quadrature Decoder Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A and phase B encoding mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Count and direction encoding mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBPOL</name>
|
|
<description>Phase B Input Polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAPOL</name>
|
|
<description>Phase A Input Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHBFLTREN</name>
|
|
<description>Phase B Input Filter Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase B input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase B input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PHAFLTREN</name>
|
|
<description>Phase A Input Filter Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Phase A input filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Phase A input filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CONF</name>
|
|
<description>Configuration</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LDFQ</name>
|
|
<description>Load Frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BDMMODE</name>
|
|
<description>Debug Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GTBEEN</name>
|
|
<description>Global Time Base Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Use of an external global time base is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Use of an external global time base is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GTBEOUT</name>
|
|
<description>Global Time Base Output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A global time base signal generation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A global time base signal generation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ITRIGR</name>
|
|
<description>Initialization trigger on Reload Point</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Initialization trigger is generated on counter wrap events.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Initialization trigger is generated when a reload point is reached.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTPOL</name>
|
|
<description>FTM Fault Input Polarity</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLT0POL</name>
|
|
<description>Fault Input 0 Polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT1POL</name>
|
|
<description>Fault Input 1 Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT2POL</name>
|
|
<description>Fault Input 2 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLT3POL</name>
|
|
<description>Fault Input 3 Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The fault input polarity is active high. A 1 at the fault input indicates a fault.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The fault input polarity is active low. A 0 at the fault input indicates a fault.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCONF</name>
|
|
<description>Synchronization Configuration</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HWTRIGMODE</name>
|
|
<description>Hardware Trigger Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CNTINC</name>
|
|
<description>CNTIN Register Synchronization</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNTIN register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNTIN register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVC</name>
|
|
<description>INVCTRL Register Synchronization</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>INVCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>INVCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOC</name>
|
|
<description>SWOCTRL Register Synchronization</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SWOCTRL register is updated with its buffer value at all rising edges of system clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SWOCTRL register is updated with its buffer value by the PWM synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMODE</name>
|
|
<description>Synchronization Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Legacy PWM synchronization is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enhanced PWM synchronization is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTCNT</name>
|
|
<description>FTM counter synchronization is activated by the software trigger.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWWRBUF</name>
|
|
<description>MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWOM</name>
|
|
<description>Output mask synchronization is activated by the software trigger.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWINVC</name>
|
|
<description>Inverting control synchronization is activated by the software trigger.</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWSOC</name>
|
|
<description>Software output control synchronization is activated by the software trigger.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWRSTCNT</name>
|
|
<description>FTM counter synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the FTM counter synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the FTM counter synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWWRBUF</name>
|
|
<description>MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWOM</name>
|
|
<description>Output mask synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the OUTMASK register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the OUTMASK register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWINVC</name>
|
|
<description>Inverting control synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the INVCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the INVCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HWSOC</name>
|
|
<description>Software output control synchronization is activated by a hardware trigger.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A hardware trigger does not activate the SWOCTRL register synchronization.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A hardware trigger activates the SWOCTRL register synchronization.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVCTRL</name>
|
|
<description>FTM Inverting Control</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INV0EN</name>
|
|
<description>Pair Channels 0 Inverting Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV1EN</name>
|
|
<description>Pair Channels 1 Inverting Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV2EN</name>
|
|
<description>Pair Channels 2 Inverting Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INV3EN</name>
|
|
<description>Pair Channels 3 Inverting Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Inverting is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverting is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWOCTRL</name>
|
|
<description>FTM Software Output Control</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OC</name>
|
|
<description>Channel 0 Software Output Control Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OC</name>
|
|
<description>Channel 1 Software Output Control Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OC</name>
|
|
<description>Channel 2 Software Output Control Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OC</name>
|
|
<description>Channel 3 Software Output Control Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OC</name>
|
|
<description>Channel 4 Software Output Control Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OC</name>
|
|
<description>Channel 5 Software Output Control Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OC</name>
|
|
<description>Channel 6 Software Output Control Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OC</name>
|
|
<description>Channel 7 Software Output Control Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The channel output is not affected by software output control.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The channel output is affected by software output control.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0OCV</name>
|
|
<description>Channel 0 Software Output Control Value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1OCV</name>
|
|
<description>Channel 1 Software Output Control Value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2OCV</name>
|
|
<description>Channel 2 Software Output Control Value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3OCV</name>
|
|
<description>Channel 3 Software Output Control Value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4OCV</name>
|
|
<description>Channel 4 Software Output Control Value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5OCV</name>
|
|
<description>Channel 5 Software Output Control Value</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6OCV</name>
|
|
<description>Channel 6 Software Output Control Value</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7OCV</name>
|
|
<description>Channel 7 Software Output Control Value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The software output control forces 0 to the channel output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The software output control forces 1 to the channel output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMLOAD</name>
|
|
<description>FTM PWM Load</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CH0SEL</name>
|
|
<description>Channel 0 Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH1SEL</name>
|
|
<description>Channel 1 Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH2SEL</name>
|
|
<description>Channel 2 Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH3SEL</name>
|
|
<description>Channel 3 Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH4SEL</name>
|
|
<description>Channel 4 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH5SEL</name>
|
|
<description>Channel 5 Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH6SEL</name>
|
|
<description>Channel 6 Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH7SEL</name>
|
|
<description>Channel 7 Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Channel match is not included as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Channel match is included as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HCSEL</name>
|
|
<description>Half Cycle Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Half cycle reload is disabled and it is not considered as a reload opportunity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Half cycle reload is enabled and it is considered as a reload opportunity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LDOK</name>
|
|
<description>Load Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Loading updated values is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loading updated values is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GLEN</name>
|
|
<description>Global Load Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Global Load Ok disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GLDOK</name>
|
|
<description>Global Load OK</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No action.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LDOK bit is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCR</name>
|
|
<description>Half Cycle Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HCVAL</name>
|
|
<description>Half Cycle Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MOD_MIRROR</name>
|
|
<description>Modulo</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACMOD</name>
|
|
<description>Fractional Value for MOD register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOD</name>
|
|
<description>Modulo Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3,4,5,6,7</dimIndex>
|
|
<name>C%sV_MIRROR</name>
|
|
<description>Channel (n) Value</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FRACVAL</name>
|
|
<description>Fractional Value for VAL register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VAL</name>
|
|
<description>Channel Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Secure Real Time Clock</description>
|
|
<prependToName>RTC_</prependToName>
|
|
<baseAddress>0x4003D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x808</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TSR</name>
|
|
<description>RTC Time Seconds Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSR</name>
|
|
<description>Time Seconds Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPR</name>
|
|
<description>RTC Time Prescaler Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TPR</name>
|
|
<description>Time Prescaler Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAR</name>
|
|
<description>RTC Time Alarm Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAR</name>
|
|
<description>Time Alarm Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCR</name>
|
|
<description>RTC Time Compensation Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCR</name>
|
|
<description>Time Compensation Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10000000</name>
|
|
<description>Time Prescaler Register overflows every 32896 clock cycles.</description>
|
|
<value>#10000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111111</name>
|
|
<description>Time Prescaler Register overflows every 32769 clock cycles.</description>
|
|
<value>#11111111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time Prescaler Register overflows every 32768 clock cycles.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time Prescaler Register overflows every 32767 clock cycles.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111111</name>
|
|
<description>Time Prescaler Register overflows every 32641 clock cycles.</description>
|
|
<value>#1111111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIR</name>
|
|
<description>Compensation Interval Register</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCV</name>
|
|
<description>Time Compensation Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CIC</name>
|
|
<description>Compensation Interval Counter</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>RTC Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SWR</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by POR and by software explicitly clearing it.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPE</name>
|
|
<description>Wakeup Pin Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Wakeup pin is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUP</name>
|
|
<description>Supervisor Access</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Non-supervisor mode write accesses are not supported and generate a bus error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Non-supervisor mode write accesses are supported.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UM</name>
|
|
<description>Update Mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Registers cannot be written when locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Registers can be written when locked under limited conditions.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPS</name>
|
|
<description>Wakeup Pin Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPS</name>
|
|
<description>Clock Pin Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The RTC 32kHz crystal clock is output on RTC_CLKOUT.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPOS</name>
|
|
<description>LPO Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTC prescaler increments using 32 kHz crystal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTC prescaler increments using 128 kHz LPO, bits [4:0] of the prescaler are bypassed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSCE</name>
|
|
<description>Oscillator Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>32.768 kHz oscillator is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKO</name>
|
|
<description>Clock Output</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The 32 kHz clock is allowed to output on RTC_CLKOUT.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The 32 kHz clock is not allowed to output on RTC_CLKOUT.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPE</name>
|
|
<description>Clock Pin Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>RTC_CLKOUT is disabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>RTC_CLKOUT is enabled.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>RTC Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Time Invalid Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time is valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time is invalid and time counter is read as zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Time Overflow Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time overflow has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time overflow has occurred and time counter is read as zero.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAF</name>
|
|
<description>Time Alarm Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time alarm has not occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time alarm has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCE</name>
|
|
<description>Time Counter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time counter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time counter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LR</name>
|
|
<description>RTC Lock Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TCL</name>
|
|
<description>Time Compensation Lock</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time Compensation Register is locked and writes are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time Compensation Register is not locked and writes complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRL</name>
|
|
<description>Control Register Lock</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Control Register is locked and writes are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Control Register is not locked and writes complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRL</name>
|
|
<description>Status Register Lock</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Status Register is locked and writes are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Status Register is not locked and writes complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRL</name>
|
|
<description>Lock Register Lock</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Lock Register is locked and writes are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Lock Register is not locked and writes complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>RTC Interrupt Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIIE</name>
|
|
<description>Time Invalid Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time invalid flag does not generate an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time invalid flag does generate an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>Time Overflow Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time overflow flag does not generate an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time overflow flag does generate an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>Time Alarm Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time alarm flag does not generate an interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Time alarm flag does generate an interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSIE</name>
|
|
<description>Time Seconds Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Seconds interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Seconds interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WPON</name>
|
|
<description>Wakeup Pin On</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If the wakeup pin is enabled, then the wakeup pin will assert.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSIC</name>
|
|
<description>Timer Seconds Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 Hz.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 Hz.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>4 Hz.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>8 Hz.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>16 Hz.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>32 Hz.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>64 Hz.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>128 Hz.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WAR</name>
|
|
<description>RTC Write Access Register</description>
|
|
<addressOffset>0x800</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSRW</name>
|
|
<description>Time Seconds Register Write</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the Time Seconds Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the Time Seconds Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPRW</name>
|
|
<description>Time Prescaler Register Write</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the Time Prescaler Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the Time Prescaler Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TARW</name>
|
|
<description>Time Alarm Register Write</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the Time Alarm Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the Time Alarm Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCRW</name>
|
|
<description>Time Compensation Register Write</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the Time Compensation Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the Time Compensation Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRW</name>
|
|
<description>Control Register Write</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the Control Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the Control Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRW</name>
|
|
<description>Status Register Write</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the Status Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the Status Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRW</name>
|
|
<description>Lock Register Write</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the Lock Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the Lock Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IERW</name>
|
|
<description>Interrupt Enable Register Write</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the Interupt Enable Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the Interrupt Enable Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAR</name>
|
|
<description>RTC Read Access Register</description>
|
|
<addressOffset>0x804</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSRR</name>
|
|
<description>Time Seconds Register Read</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the Time Seconds Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the Time Seconds Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPRR</name>
|
|
<description>Time Prescaler Register Read</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the Time Pprescaler Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the Time Prescaler Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TARR</name>
|
|
<description>Time Alarm Register Read</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the Time Alarm Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the Time Alarm Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCRR</name>
|
|
<description>Time Compensation Register Read</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the Time Compensation Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the Time Compensation Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CRR</name>
|
|
<description>Control Register Read</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the Control Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the Control Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRR</name>
|
|
<description>Status Register Read</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the Status Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the Status Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LRR</name>
|
|
<description>Lock Register Read</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the Lock Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the Lock Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IERR</name>
|
|
<description>Interrupt Enable Register Read</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads to the Interrupt Enable Register are ignored.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reads to the Interrupt Enable Register complete as normal.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPTMR0</name>
|
|
<description>Low Power Timer</description>
|
|
<prependToName>LPTMR0_</prependToName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PWT_LPTMR0</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>Low Power Timer Control Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPTMR is disabled and internal logic is reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPTMR is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TMS</name>
|
|
<description>Timer Mode Select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Time Counter mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulse Counter mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TFC</name>
|
|
<description>Timer Free-Running Counter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CNR is reset whenever TCF is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CNR is reset on overflow.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPP</name>
|
|
<description>Timer Pin Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TPS</name>
|
|
<description>Timer Pin Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Pulse counter input 0 is selected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Pulse counter input 1 is selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Pulse counter input 2 is selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Pulse counter input 3 is selected.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Timer Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Timer Compare Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The value of CNR is not equal to CMR and increments.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The value of CNR is equal to CMR and increments.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Timer DMA Request Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer DMA Request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer DMA Request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<description>Low Power Timer Prescale Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Prescaler Clock Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Prescaler/glitch filter clock 0 selected.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Prescaler/glitch filter clock 1 selected.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Prescaler/glitch filter clock 2 selected.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Prescaler/glitch filter clock 3 selected.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PBYP</name>
|
|
<description>Prescaler Bypass</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Prescaler/glitch filter is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Prescaler/glitch filter is bypassed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescale Value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMR</name>
|
|
<description>Low Power Timer Compare Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPARE</name>
|
|
<description>Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNR</name>
|
|
<description>Low Power Timer Counter Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COUNTER</name>
|
|
<description>Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TSI</name>
|
|
<description>Touch sense input</description>
|
|
<prependToName>TSI_</prependToName>
|
|
<baseAddress>0x40045000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x28</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TSI</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>GENCS</name>
|
|
<description>TSI General Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EOSDMEO</name>
|
|
<description>End-of-Scan DMA Transfer Request Enable Only</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EOSF</name>
|
|
<description>End of Scan Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Scan not complete.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Scan complete.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCNIP</name>
|
|
<description>Scan In Progress Status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No scan in progress.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Scan in progress.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STM</name>
|
|
<description>Scan Trigger Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software trigger scan.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware trigger scan.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STPE</name>
|
|
<description>TSI STOP Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TSI is disabled when MCU goes into low power mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Allows TSI to continue running in all low power modes.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSIIEN</name>
|
|
<description>Touch Sensing Input Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TSI interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TSI interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSIEN</name>
|
|
<description>Touch Sensing Input Module Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TSI module disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TSI module enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKSOC_SEL</name>
|
|
<description>CLKSOC_SEL</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RUN_CTRL</name>
|
|
<description>RUN_CTRL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSI_ANA_TEST</name>
|
|
<description>TSI_ANA_TEST</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DVOLT</name>
|
|
<description>DVOLT</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Vm=0.3V; Vp=1.3V; dvolt=1.0V.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Vm=0.3V; Vp=1.6V; dvolt=1.3V.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Vm=0.3V; Vp=1.9V; dvolt=1.6V.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Vm=0.3V; Vp=2.3V; dvolt=2.0V.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESOR</name>
|
|
<description>End-of-scan or Out-of-Range Interrupt Selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Out-of-range interrupt is allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>End-of-scan interrupt is allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OUTRGF</name>
|
|
<description>Out of Range Flag.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>TSI DATA Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSICNT</name>
|
|
<description>TSI Conversion Counter Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWTS</name>
|
|
<description>Software Trigger Start</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start a scan to determine which channel is specified by TSI_DATA[TSICH].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Transfer Enabled</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSICH</name>
|
|
<description>TSICH</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>For self-cap mode: Channel 0.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>For self-cap mode: Channel 1.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>For self-cap mode: Channel 2.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>For self-cap mode: Channel 3.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>For self-cap mode: Channel 4.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>For self-cap mode: Channel 5.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>For self-cap mode: Channel 6.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>For self-cap mode: Channel 7.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>For self-cap mode: Channel 8.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>For self-cap mode: Channel 9.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>For self-cap mode: Channel 10.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>For self-cap mode: Channel 11.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>For self-cap mode: Channel 12.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>For self-cap mode: Channel 13.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>For self-cap mode: Channel 14.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>For self-cap mode: Channel 15.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>For self-cap mode: Channel 16.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>For self-cap mode: Channel 17.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>For self-cap mode: Channel 18.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>For self-cap mode: Channel 19.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>For self-cap mode: Channel 20.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>For self-cap mode: Channel 21.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>For self-cap mode: Channel 22.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>For self-cap mode: Channel 23.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>For self-cap mode: Channel 24.</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSHD</name>
|
|
<description>TSI Threshold Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>THRESL</name>
|
|
<description>TSI Wakeup Channel Low-threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>THRESH</name>
|
|
<description>TSI Wakeup Channel High-threshold</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODE</name>
|
|
<description>TSI MODE Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3C0060</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>S_NOISE</name>
|
|
<description>S_NOISE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>noise cancellation off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>noise cancellation on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>MODE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>self-cap mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>mutual-cap mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SETCLK</name>
|
|
<description>SETCLK</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>20.72MHz.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>16.65MHz.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>13.87MHz.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>11.91MHz.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_XCH</name>
|
|
<description>S_XCH</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1/16.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1/8.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>1/4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>1/2.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>NA.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>NA.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>NA.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>NA.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_XIN</name>
|
|
<description>S_XIN</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>1/8.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1/4.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_CTRIM</name>
|
|
<description>Capacitor trim setting</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Ctrim=2.5p.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Ctrim=5.0p.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Ctrim=7.5p.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Ctrim=10p.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Ctrim=12.5p.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Ctrim=15p.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Ctrim=17.5p.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Ctrim=20p.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_SEN</name>
|
|
<description>S_SEN</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sensitivity boost off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sensitivity boost on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_W_SHIELD</name>
|
|
<description>S_W_SHIELD</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>shield switch off.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>shield switch on.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>S_XDN</name>
|
|
<description>S_XDN</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1/16.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1/8.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>1/4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>1/2.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>NA.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>NA.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>NA.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>NA.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MUL0</name>
|
|
<description>TSI MUTUAL-CAP Register 0</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x60006300</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M_SEL_RX</name>
|
|
<description>M_SEL_RX</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>select channel 6 as rx6.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>select channel 7 as rx7.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>select channel 8 as rx8.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>select channel 9 as rx9.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>select channel 10 as rx10.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>select channel 11 as rx11.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>NA.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>NA.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_SEL_TX</name>
|
|
<description>M_SEL_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>select channel 0 as tx0.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>select channel 1 as tx1.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>select channel 2 as tx2.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>select channel 3 as tx3.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>select channel 4 as tx4.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>select channel 5 as tx5.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>NA.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>NA.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_SEN_RES</name>
|
|
<description>M_SEN_RES</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>2.5k.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>5k.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>7.5k.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>10k.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>12.5k.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>15k.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>17.5k.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>20k.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>22.5k.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>25k.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>27.5k.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>30k.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>32.5k.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>35k.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>37.5k.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>40k.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_PRE_RES</name>
|
|
<description>M_PRE_RES</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1k.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2k.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3k.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4k.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5k.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6k.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7k.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8k.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_PRE_CURRENT</name>
|
|
<description>M_PRE_CURRENT</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1uA.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2uA.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>3uA.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>4uA.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>5uA.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>6uA.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>7uA.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>8uA.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MUL1</name>
|
|
<description>TSI MUTUAL-CAP Register 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5007E</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>M_NMIR_CTRL</name>
|
|
<description>M_NMIR_CTRL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable nmos mirror.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable nmos mirror.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_NMIRROR</name>
|
|
<description>M_NMIRROR</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>m=1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>m=2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>m=3.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>m=4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_PMIRRORR</name>
|
|
<description>M_PMIRRORR</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>m=1.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>m=2.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>m=3.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>m=4.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_PMIRRORL</name>
|
|
<description>M_PMIRRORL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>m=4.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>m=8.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>m=12.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>m=16.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>m=20.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>m=24.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>m=28.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>m=32.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_VPRE_CHOOSE</name>
|
|
<description>M_VPRE_CHOOSE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal 1.2V voltage.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>1.2V PMC output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_MODE</name>
|
|
<description>M_MODE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>-5V~+5V.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>0V~+5V.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M_SEN_BOOST</name>
|
|
<description>M_SEN_BOOST</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>0u.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>2u.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>4u.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>6u.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>8u.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>10u.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>12u.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>14u</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>16u.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>18u.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>20u.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>22u.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>24u.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>26u.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>28u.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>30u.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>32u.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>34u.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>36u.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>38u.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>40u.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>42u.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>44u.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>46u.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>48u.</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>50u.</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>52u.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>54u.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>56u.</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>58u.</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>60u.</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>62u.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SINC</name>
|
|
<description>TSI SINC filter Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x70001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSC_CONTROL_OUT</name>
|
|
<description>SSC_CONTROL_OUT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSC output value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSC output value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SINC_VALID</name>
|
|
<description>SINC_VALID</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SINC filter is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SINC filter is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SINC_OVERFLOW_FLAG</name>
|
|
<description>SINC_OVERFLOW_FLAG</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The counter result has no overflow occurence in the last scan process.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The counter result has an overflow occurence in the last scan process.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWITCH_ENABLE</name>
|
|
<description>SWITCH_ENABLE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SSC function is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SSC function is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DECIMATION</name>
|
|
<description>DECIMATION</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 1 scan period.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 2 scan periods.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 3 scan periods.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 4 scan periods.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 5 scan periods.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 6 scan periods.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 7 scan periods.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 8 scan periods.</description>
|
|
<value>#00111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01000</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 9 scan periods.</description>
|
|
<value>#01000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01001</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 10 scan periods.</description>
|
|
<value>#01001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01010</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 11 scan periods.</description>
|
|
<value>#01010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01011</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 12 scan periods.</description>
|
|
<value>#01011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01100</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 13 scan periods.</description>
|
|
<value>#01100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01101</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 14 scan periods.</description>
|
|
<value>#01101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01110</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 15 scan periods.</description>
|
|
<value>#01110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 16 scan periods.</description>
|
|
<value>#01111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10000</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 17 scan periods.</description>
|
|
<value>#10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10001</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 18 scan periods.</description>
|
|
<value>#10001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10010</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 19 scan periods.</description>
|
|
<value>#10010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10011</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 20 scan periods.</description>
|
|
<value>#10011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10100</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 21 scan periods.</description>
|
|
<value>#10100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10101</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 22 scan periods.</description>
|
|
<value>#10101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10110</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 23 scan periods.</description>
|
|
<value>#10110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10111</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 24 scan periods.</description>
|
|
<value>#10111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11000</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 25 scan periods.</description>
|
|
<value>#11000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11001</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 26 scan periods.</description>
|
|
<value>#11001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11010</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 27 scan periods.</description>
|
|
<value>#11010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11011</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 28 scan periods.</description>
|
|
<value>#11011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11100</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 29 scan periods.</description>
|
|
<value>#11100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11101</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 30 scan periods.</description>
|
|
<value>#11101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11110</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 31 scan periods.</description>
|
|
<value>#11110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111</name>
|
|
<description>The TSI_DATA[TSICNT] bits is the counter value of 32 scan periods.</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORDER</name>
|
|
<description>ORDER</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Using 1 order sinc filter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Using 2 order sinc filter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CUTOFF</name>
|
|
<description>CUTOFF</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>div=1.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>div=2.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>div=4.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>div=8.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>div=16.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>div=32.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>div=64.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>div=128.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>NC.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>NC.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>NC.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>NC.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>NC.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>NC</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>NC.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>NC.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSC0</name>
|
|
<description>TSI SSC Register 0</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x60320000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSC_PRESCALE_NUM</name>
|
|
<description>SSC_PRESCALE_NUM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000000</name>
|
|
<description>div2(2^0*2)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00000001</name>
|
|
<description>div4(2^1*2)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00000011</name>
|
|
<description>div8(2^2*2)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00000111</name>
|
|
<description>div16(2^3*2)</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001111</name>
|
|
<description>div32(2^4*2)</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011111</name>
|
|
<description>div64(2^5*2)</description>
|
|
<value>#11111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00111111</name>
|
|
<description>div128(2^6*2)</description>
|
|
<value>#111111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01111111</name>
|
|
<description>div256(2^7*2)</description>
|
|
<value>#1111111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11111111</name>
|
|
<description>div512(2^8*2)</description>
|
|
<value>#11111111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BASE_NOCHARGE_NUM</name>
|
|
<description>BASE_NOCHARGE_NUM</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>The SSC output bit 1's basic period will be 1 clock cycle of system clock.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>The SSC output bit 1's basic period will be 2 clock cycles of system clock.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>The SSC output bit 1's basic period will be 3 clock cycles of system clock.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>The SSC output bit 1's basic period will be 4 clock cycles of system clock.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>The SSC output bit 1's basic period will be 5 clock cycles of system clock.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>The SSC output bit 1's basic period will be 6 clock cycles of system clock.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>The SSC output bit 1's basic period will be 7 clock cycles of system clock.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>The SSC output bit 1's basic period will be 8 clock cycles of system clock.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>The SSC output bit 1's basic period will be 9 clock cycles of system clock.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>The SSC output bit 1's basic period will be 10 clock cycles of system clock.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>The SSC output bit 1's basic period will be 11 clock cycles of system clock.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>The SSC output bit 1's basic period will be 12 clock cycles of system clock.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>The SSC output bit 1's basic period will be 13 clock cycles of system clock.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>The SSC output bit 1's basic period will be 14 clock cycles of system clock.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>The SSC output bit 1's basic period will be 15 clock cycles of system clock.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>The SSC output bit 1's basic period will be 16 clock cycles of system clock.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHARGE_NUM</name>
|
|
<description>CHARGE_NUM</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>The SSC output bit 0's period will be 1 clock cycle of system clock.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>The SSC output bit 0's period will be 2 clock cycles of system clock.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>The SSC output bit 0's period will be 3 clock cycles of system clock.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>The SSC output bit 0's period will be 4 clock cycles of system clock.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>The SSC output bit 0's period will be 5 clock cycles of system clock.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>The SSC output bit 0's period will be 6 clock cycles of system clock.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>The SSC output bit 0's period will be 7 clock cycles of system clock.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>The SSC output bit 0's period will be 8 clock cycles of system clock.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>The SSC output bit 0's period will be 9 clock cycles of system clock.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>The SSC output bit 0's period will be 10 clock cycles of system clock.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>The SSC output bit 0's period will be 11 clock cycles of system clock.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>The SSC output bit 0's period will be 12 clock cycles of system clock.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>The SSC output bit 0's period will be 13 clock cycles of system clock.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>The SSC output bit 0's period will be 14 clock cycles of system clock.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>The SSC output bit 0's period will be 15 clock cycles of system clock.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>The SSC output bit 0's period will be 16 clock cycles of system clock.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSC_CONTROL_REVERSE</name>
|
|
<description>SSC_CONTROL_REVERSE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Keep the polarity of the SSC output bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reverse the polarity of the SSC output bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSC_MODE</name>
|
|
<description>SSC_MODE</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Using PRBS method generating SSC output bit.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Using up-down counter generating SSC output bit.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>SSC function is disabled.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>NC.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRBS_OUTSEL</name>
|
|
<description>PRBS_OUTSEL</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>NC.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>NC.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>The length of the PRBS is 2.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>The length of the PRBS is 3.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>The length of the PRBS is 4.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>The length of the PRBS is 5.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>The length of the PRBS is 6.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>The length of the PRBS is 7.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>The length of the PRBS is 8.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>The length of the PRBS is 9.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>The length of the PRBS is 10.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>The length of the PRBS is 11.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>The length of the PRBS is 12.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>The length of the PRBS is 13.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>The length of the PRBS is 14.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>The length of the PRBS is 15.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSC1</name>
|
|
<description>TSI SSC Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x600040</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRBS_SEED_LO</name>
|
|
<description>PRBS_SEED_LO</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRBS_SEED_HI</name>
|
|
<description>PRBS_SEED_HI</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRBS_WEIGHT_LO</name>
|
|
<description>PRBS_WEIGHT_LO</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRBS_WEIGHT_HI</name>
|
|
<description>PRBS_WEIGHT_HI</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSC2</name>
|
|
<description>TSI SSC Register 2</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10080101</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MOVE_REPEAT_NUM</name>
|
|
<description>MOVE_REPEAT_NUM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00000</name>
|
|
<description>The up_down counter will be updated for every sample-charge cycle.</description>
|
|
<value>#00000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00001</name>
|
|
<description>The up_down counter will be updated for every 2 sample-charge cycles.</description>
|
|
<value>#00001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00010</name>
|
|
<description>The up_down counter will be updated for every 3 sample-charge cycles.</description>
|
|
<value>#00010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00011</name>
|
|
<description>The up_down counter will be updated for every 4 sample-charge cycles.</description>
|
|
<value>#00011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00100</name>
|
|
<description>The up_down counter will be updated for every 5 sample-charge cycles.</description>
|
|
<value>#00100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00101</name>
|
|
<description>The up_down counter will be updated for every 6 sample-charge cycles.</description>
|
|
<value>#00101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>00110</name>
|
|
<description>The up_down counter will be updated for every 7 sample-charge cycles.</description>
|
|
<value>#00110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOVE_STEPS_NUM</name>
|
|
<description>MOVE_STEPS_NUM</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>The added value for up-down counter is 0.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>The added value for up-down counter is 1.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>The added value for up-down counter is 2.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>The added value for up-down counter is 3.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>The added value for up-down counter is 4.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>The added value for up-down counter is 5.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>The added value for up-down counter is 6.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>The added value for up-down counter is 7.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MOVE_NOCHARGE_MAX</name>
|
|
<description>MOVE_NOCHARGE_MAX</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOVE_NOCHARGE_MIN</name>
|
|
<description>MOVE_NOCHARGE_MIN</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>The SSC output bit 1's min period will be (1 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycle of system clock.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>The SSC output bit 1's min period will be (2 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>The SSC output bit 1's min period will be (3 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>The SSC output bit 1's min period will be (4 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>The SSC output bit 1's min period will be (5 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>The SSC output bit 1's min period will be (6 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>The SSC output bit 1's min period will be (7 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>The SSC output bit 1's min period will be (8 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>The SSC output bit 1's min period will be (9 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>The SSC output bit 1's min period will be (10 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>The SSC output bit 1's min period will be (11 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>The SSC output bit 1's min period will be (12 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>The SSC output bit 1's min period will be (13 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>The SSC output bit 1's min period will be (14 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>The SSC output bit 1's min period will be (15 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>The SSC output bit 1's min period will be (16 + TSI_SSC0[BASE_ NOCHARGE_NUM]) clock cycles of system clock.</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SIM</name>
|
|
<description>System Integration Module</description>
|
|
<prependToName>SIM_</prependToName>
|
|
<baseAddress>0x40048000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x4</offset>
|
|
<size>0x6C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CHIPCTL</name>
|
|
<description>Chip Control register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_INTERLEAVE_EN</name>
|
|
<description>ADC interleave channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No interleave channel</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUTDIV</name>
|
|
<description>CLKOUT divider ratio</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Divided by 1</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Divided by 2</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Divided by 4</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Divided by 8</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLKOUTSEL</name>
|
|
<description>CLKOUT Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Reseved</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL), see SCG_CLKOUTCNFG register.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>RTC oscillator (OSC32) clock (32 kHz)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>LPO clock (128 kHz)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PDB_BB_SEL</name>
|
|
<description>PDB back-to-back select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB0 channel 0 back-to-back operation with ADC0 COCO[1:0] and PDB0 channel 1 back-to-back operation with ADC1 COCO[1:0]</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PDB0 Channel 0 back-to-back operation with COCO[0] of ADC0 and COCO[1] of ADC1 ; PDB0 Channel 1 back-to-back operation with COCO[0] of ADC1 and COCO[1] of ADC0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTCLKSEL</name>
|
|
<description>PWT clock source select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PWT alternative clock is from the TCLK0 pin.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PWT alternative clock is from the TCLK1 pin.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PWT alternative clock is from the TCLK2 pin.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTC32KCLKSEL</name>
|
|
<description>RTC 32K clock input select</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>OSC32 clock output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>RTC_CLKIN</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTMOPT0</name>
|
|
<description>FTM Option Register 0</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTM0FLTxSEL</name>
|
|
<description>FTM0 Fault x Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FTM0CLKSEL</name>
|
|
<description>FTM0 External Clock Pin Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM0 external clock driven by TCLK0 pin.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FTM0 external clock driven by TCLK1 pin.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FTM0 external clock driven by TCLK2 pin.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>No clock input</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1CLKSEL</name>
|
|
<description>FTM1 External Clock Pin Select</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM1 external clock driven by TCLK0 pin.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FTM1 external clock driven by TCLK1 pin.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FTM1 external clock driven by TCLK2 pin.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>No clock input</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2CLKSEL</name>
|
|
<description>FTM2 External Clock Pin Select</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM2 external clock driven by TCLK0 pin.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FTM2 external clock driven by TCLK1 pin.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>FTM2 external clock driven by TCLK2 pin.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>No clock input</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCOPT</name>
|
|
<description>ADC Options Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADC0TRGSEL</name>
|
|
<description>ADC0 trigger source select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TRGMUX output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0SWPRETRG</name>
|
|
<description>ADC0 software pre-trigger sources</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>software pre-trigger 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>software pre-trigger 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>software pre-trigger 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>software pre-trigger 3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC0PRETRGSEL</name>
|
|
<description>ADC0 pre-trigger source select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PDB output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>TRGMUX output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>ADC0 software pre-trigger</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1TRGSEL</name>
|
|
<description>ADC1 trigger source select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PDB output</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TRGMUX output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1SWPRETRG</name>
|
|
<description>ADC1 software pre-trigger sources</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>software pre-trigger 0</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>software pre-trigger 1</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>software pre-trigger 2</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>software pre-trigger 3</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC1PRETRGSEL</name>
|
|
<description>ADC1 pre-trigger source select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PDB output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>TRGMUX output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>ADC1 software pre-trigger</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTMOPT1</name>
|
|
<description>FTM Option Register 1</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FTM0SYNCBIT</name>
|
|
<description>FTM0 Sync Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write 1 to assert the TRIG1 input to FTM0. Software must clear this bit to allow other trigger sources to assert.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1SYNCBIT</name>
|
|
<description>FTM1 Sync Bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write 1 to assert the TRIG1 input to FTM1. Software must clear this bit to allow other trigger sources to assert.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2SYNCBIT</name>
|
|
<description>FTM2 Sync Bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Write 1 to assert the TRIG1 input to FTM2. Software must clear this bit to allow other trigger sources to assert.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM1CH0SEL</name>
|
|
<description>FTM1 CH0 Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM1_CH0 input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>CMP0 output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>CMP1 output</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2CH0SEL</name>
|
|
<description>FTM2 CH0 Select</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>FTM2_CH0 input</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>CMP0 output</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>CMP1 output</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM2CH1SEL</name>
|
|
<description>FTM2 CH1 Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FTM2_CH1 input</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>exclusive OR of FTM2_CH0, FTM2_CH1, and FTM1_CH1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FTM0_OUTSEL</name>
|
|
<description>FTM0 channel modulation select with FTM1_CH1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No modulation with FTM1_CH1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Modulation with FTM1_CH1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDID</name>
|
|
<description>System Device Identification Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x100</resetValue>
|
|
<resetMask>0xF80</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINID</name>
|
|
<description>Pin identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>64-pin</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>80-pin</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>100-pin</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PROJECTID</name>
|
|
<description>Project ID</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REVID</name>
|
|
<description>Device revision number</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RAMSIZE</name>
|
|
<description>RAM size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>16 KB</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>32 KB</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SERIESID</name>
|
|
<description>Kinetis Series ID</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Kinetis E+ series</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SUBFAMID</name>
|
|
<description>Kinetis E-series Sub-Family ID</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FAMILYID</name>
|
|
<description>Kinetis E-series Family ID</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>KE0x Family (Entry level)</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>KE1x Family (Enhanced features)</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>KE3x Family (with SLCD)</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCFG1</name>
|
|
<description>Flash Configuration Register 1</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xF00FFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLASHDIS</name>
|
|
<description>Flash Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flash is enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flash is disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLASHDOZE</name>
|
|
<description>Flash Doze</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Flash remains enabled during Doze mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Flash is disabled for the duration of Doze mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DEPART</name>
|
|
<description>FlexNVM partition</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EEERAMSIZE</name>
|
|
<description>EEE SRAM SIZE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>2 KB</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>1 KB</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>512 Bytes</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>256 Bytes</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>128 Bytes</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>64 Bytes</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>32 Bytes</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFSIZE</name>
|
|
<description>Program flash size</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>128 KB of program flash memory, 4 KB protection region</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>256 KB of program flash memory, 8 KB protection region</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVMSIZE</name>
|
|
<description>FlexNVM size</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>0 KB of FlexNVM</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>32 KB of FlexNVM</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCFG2</name>
|
|
<description>Flash Configuration Register 2</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MAXADDR1</name>
|
|
<description>Max address block 1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAXADDR0</name>
|
|
<description>Max address block 0</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDH</name>
|
|
<description>Unique Identification Register High</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID127_96</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDMH</name>
|
|
<description>Unique Identification Register Mid-High</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID95_64</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDML</name>
|
|
<description>Unique Identification Register Mid Low</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID63_32</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UIDL</name>
|
|
<description>Unique Identification Register Low</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UID31_0</name>
|
|
<description>Unique Identification</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISCTRL</name>
|
|
<description>Miscellaneous Control register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SW_TRG</name>
|
|
<description>Software Trigger bit to TRGMUX</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMA_INT_SEL</name>
|
|
<description>DMA channel interrupt OR select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UART0ODE</name>
|
|
<description>UART0 Open Drain Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain is disabled on UART0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain is enabled on UART0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART1ODE</name>
|
|
<description>UART1 Open Drain Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain is disabled on UART1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain is enabled on UART1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART2ODE</name>
|
|
<description>UART2 Open Drain Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain is disabled on UART2</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain is enabled on UART2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTA</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTA_</prependToName>
|
|
<baseAddress>0x40049000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTAE</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PCR0</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR1</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR2</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR3</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR4</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR5</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR6</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR7</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR8</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR9</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR10</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR11</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR12</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR13</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR14</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR15</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR16</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR17</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR18</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR19</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR20</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR21</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR22</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR23</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR24</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR25</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR26</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR27</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR28</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR29</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR30</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR31</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filters are clocked by the LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTB</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTB_</prependToName>
|
|
<baseAddress>0x4004A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTBCD</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PCR0</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR1</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR2</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR3</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR4</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR5</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR6</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR7</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR8</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR9</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR10</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR11</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR12</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR13</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR14</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR15</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR16</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR17</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR18</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR19</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR20</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR21</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR22</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR23</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR24</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR25</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR26</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR27</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR28</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR29</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR30</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR31</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filters are clocked by the LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTC</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTC_</prependToName>
|
|
<baseAddress>0x4004B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTBCD</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PCR0</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR1</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR2</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR3</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR4</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR5</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR6</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR7</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR8</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR9</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR10</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR11</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR12</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR13</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR14</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR15</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR16</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR17</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR18</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR19</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR20</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR21</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR22</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR23</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR24</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR25</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR26</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR27</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR28</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR29</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR30</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR31</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filters are clocked by the LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTD</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTD_</prependToName>
|
|
<baseAddress>0x4004C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTBCD</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PCR0</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR1</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR2</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR3</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR4</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR5</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR6</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR7</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR8</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR9</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR10</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR11</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR12</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR13</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR14</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR15</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR16</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR17</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR18</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR19</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR20</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR21</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR22</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR23</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR24</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR25</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR26</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR27</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR28</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR29</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR30</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR31</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filters are clocked by the LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PORTE</name>
|
|
<description>Pin Control and Interrupts</description>
|
|
<groupName>PORT</groupName>
|
|
<prependToName>PORTE_</prependToName>
|
|
<baseAddress>0x4004D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xCC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTAE</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PCR0</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR1</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR2</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR3</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR4</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR5</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR6</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR7</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR8</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR9</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR10</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR11</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR12</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR13</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR14</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR15</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR16</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR17</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR18</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR19</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR20</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR21</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR22</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR23</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR24</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR25</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR26</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR27</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR28</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR29</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR30</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR31</name>
|
|
<description>Pin Control Register n</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Pull Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Pull Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Internal pullup or pulldown resistor is not enabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Slew Rate Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PFE</name>
|
|
<description>Passive Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Passive input filter is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ODE</name>
|
|
<description>Open Drain Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Open drain output is disabled on the corresponding pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DSE</name>
|
|
<description>Drive Strength Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High drive strength is configured on the corresponding pin, if pin is configured as a digital output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>Pin Mux Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Pin disabled (Alternative 0) (analog).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Alternative 1 (GPIO).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Alternative 2 (chip-specific).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Alternative 3 (chip-specific).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Alternative 4 (chip-specific).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Alternative 5 (chip-specific).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Alternative 6 (chip-specific).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Alternative 7 (chip-specific).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Control Register fields [15:0] are not locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IRQC</name>
|
|
<description>Interrupt Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Interrupt Status Flag (ISF) is disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>ISF flag and DMA request on rising edge.</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>ISF flag and DMA request on falling edge.</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>ISF flag and DMA request on either edge.</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>ISF flag and Interrupt when logic 0.</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>ISF flag and Interrupt on rising-edge.</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>ISF flag and Interrupt on falling-edge.</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>ISF flag and Interrupt on either edge.</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>ISF flag and Interrupt when logic 1.</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCLR</name>
|
|
<description>Global Pin Control Low Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPCHR</name>
|
|
<description>Global Pin Control High Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>GPWD</name>
|
|
<description>Global Pin Write Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GPWE</name>
|
|
<description>Global Pin Write Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding Pin Control Register is not updated with the value in GPWD.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding Pin Control Register is updated with the value in GPWD.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISFR</name>
|
|
<description>Interrupt Status Flag Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ISF</name>
|
|
<description>Interrupt Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configured interrupt is not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFER</name>
|
|
<description>Digital Filter Enable Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DFE</name>
|
|
<description>Digital Filter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFCR</name>
|
|
<description>Digital Filter Clock Register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Digital filters are clocked by the bus clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Digital filters are clocked by the LPO clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DFWR</name>
|
|
<description>Digital Filter Width Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FILT</name>
|
|
<description>Filter Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WDOG</name>
|
|
<description>Watchdog timer</description>
|
|
<prependToName>WDOG_</prependToName>
|
|
<baseAddress>0x40052000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDOG_EWM</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CS</name>
|
|
<description>Watchdog Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2980</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog disabled in chip stop mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog enabled in chip stop mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAIT</name>
|
|
<description>Wait Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog disabled in chip wait mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog enabled in chip wait mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBG</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog disabled in chip debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog enabled in chip debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TST</name>
|
|
<description>Watchdog Test</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Watchdog test mode disabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Allow updates</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INT</name>
|
|
<description>Watchdog Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog interrupts are disabled. Watchdog resets are not delayed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Watchdog Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Watchdog disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Watchdog enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CLK</name>
|
|
<description>Watchdog Clock</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Bus clock</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>LPO clock (128k LPO, 32k LPO, 1k LPO, or 32k OSC), whose selection is controlled via SIM_LPOCLKS[LPOCLKSEL].</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>System oscillator clock (SOSC, from SCG)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Slow internal reference clock (SIRC, from SCG)</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RCS</name>
|
|
<description>Reconfiguration Success</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reconfiguring WDOG.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reconfiguration is successful.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ULK</name>
|
|
<description>Unlock status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>WDOG is locked.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>WDOG is unlocked.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRES</name>
|
|
<description>Watchdog prescaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>256 prescaler disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>256 prescaler enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CMD32EN</name>
|
|
<description>Enables or disables WDOG support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables support for 32-bit (or 16-bit or 8-bit) refresh/unlock command write words</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FLG</name>
|
|
<description>Watchdog Interrupt Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No interrupt occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An interrupt occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WIN</name>
|
|
<description>Watchdog Window</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Window mode disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Window mode enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>Watchdog Counter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNTLOW</name>
|
|
<description>Low byte of the Watchdog Counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTHIGH</name>
|
|
<description>High byte of the Watchdog Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOVAL</name>
|
|
<description>Watchdog Timeout Value Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x400</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TOVALLOW</name>
|
|
<description>Low byte of the timeout value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TOVALHIGH</name>
|
|
<description>High byte of the timeout value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WIN</name>
|
|
<description>Watchdog Window Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WINLOW</name>
|
|
<description>Low byte of Watchdog Window</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WINHIGH</name>
|
|
<description>High byte of Watchdog Window</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWT</name>
|
|
<description>Pulse Width Timer</description>
|
|
<prependToName>PWT_</prependToName>
|
|
<baseAddress>0x40056000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PWT_LPTMR0</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CS</name>
|
|
<description>Pulse Width Timer Control and Status Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWTOV</name>
|
|
<description>PWT Counter Overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PWT counter no overflow.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PWT counter runs from 0xFFFF to 0x0000.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTRDY</name>
|
|
<description>PWT Pulse Width Valid</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PWT pulse width register(s) is not up-to-date.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>PWT pulse width register(s) has been updated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FCTLE</name>
|
|
<description>First counter load enable after enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Do not load the first counter values to corresponding registers</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Load the first coutner value to corresponding registers depended by the PWTIN level</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTSR</name>
|
|
<description>PWT Soft Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No action taken.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writing 1 to this field will perform soft reset to PWT.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POVIE</name>
|
|
<description>PWT Counter Overflow Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable PWT to generate interrupt when PWTOV is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable PWT to generate interrupt when PWTOV is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PRDYIE</name>
|
|
<description>PWT Pulse Width Data Ready Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable PWT to generate interrupt when PWTRDY is set.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable PWT to generate interrupt when PWTRDY is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTIE</name>
|
|
<description>PWT Module Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables the PWT to generate interrupt.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables the PWT to generate interrupt.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWTEN</name>
|
|
<description>PWT Module Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The PWT is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The PWT is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>Pulse Width Timer Control Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRE</name>
|
|
<description>PWT Clock Prescaler (CLKPRE) Setting</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock divided by 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Clock divided by 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Clock divided by 4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Clock divided by 8.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Clock divided by 16.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Clock divided by 32.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Clock divided by 64.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Clock divided by 128.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVL</name>
|
|
<description>PWTIN Level when Overflows</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TGL</name>
|
|
<description>PWTIN states Toggled from last state</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The selected PWTIN hasn't changed its original states from last time.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The selected PWTIN has toggled its states.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINSEL</name>
|
|
<description>PWT Pulse Inputs Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>PWTIN[0] is enabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PWTIN[1] is enabled.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PWTIN[2] enabled.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>PWTIN[3] enabled.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCLKS</name>
|
|
<description>PWT Clock Source Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>BUS_CLK is selected as the clock source of PWT counter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Alternative clock is selected as the clock source of PWT counter.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPH</name>
|
|
<description>Pulse Width Timer Positive Pulse Width Register: High</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PPWH</name>
|
|
<description>Positive Pulse Width[15:8]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PPL</name>
|
|
<description>Pulse Width Timer Positive Pulse Width Register: Loq</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PPWL</name>
|
|
<description>Positive Pulse Width[7:0]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPH</name>
|
|
<description>Pulse Width Timer Negative Pulse Width Register: High</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NPWH</name>
|
|
<description>Negative Pulse Width[15:8]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPL</name>
|
|
<description>Pulse Width Timer Negative Pulse Width Register: Low</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>NPWL</name>
|
|
<description>Negative Pulse Width[7:0]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTH</name>
|
|
<description>Pulse Width Timer Counter Register: High</description>
|
|
<addressOffset>0x6</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWTH</name>
|
|
<description>PWT counter[15:8]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTL</name>
|
|
<description>Pulse Width Timer Counter Register: Low</description>
|
|
<addressOffset>0x7</addressOffset>
|
|
<size>8</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PWTL</name>
|
|
<description>PWT counter[7:0]</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLEXIO</name>
|
|
<description>The FLEXIO Memory Map/Register Definition can be found here.</description>
|
|
<prependToName>FLEXIO_</prependToName>
|
|
<baseAddress>0x4005A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x510</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLEXIO</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1010000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Specification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard features implemented.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Supports state, logic and parallel modes.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4080404</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTER</name>
|
|
<description>Shifter Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER</name>
|
|
<description>Timer Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>Pin Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIGGER</name>
|
|
<description>Trigger Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>FlexIO Control Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FLEXEN</name>
|
|
<description>FlexIO Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FlexIO module is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FlexIO module is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Software reset is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Software reset is enabled, all FlexIO registers except the Control Register are reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FASTACC</name>
|
|
<description>Fast Access</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures for normal register accesses to FlexIO</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures for fast register accesses to FlexIO</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGE</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FlexIO is disabled in debug modes.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FlexIO is enabled in debug modes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FlexIO enabled in Doze modes.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FlexIO disabled in Doze modes.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIN</name>
|
|
<description>Pin State Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Pin Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTSTAT</name>
|
|
<description>Shifter Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSF</name>
|
|
<description>Shifter Status Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Status flag is clear</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Status flag is set</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTERR</name>
|
|
<description>Shifter Error Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEF</name>
|
|
<description>Shifter Error Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Shifter Error Flag is clear</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shifter Error Flag is set</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMSTAT</name>
|
|
<description>Timer Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSF</name>
|
|
<description>Timer Status Flags</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer Status Flag is clear</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer Status Flag is set</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTSIEN</name>
|
|
<description>Shifter Status Interrupt Enable</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSIE</name>
|
|
<description>Shifter Status Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Shifter Status Flag interrupt disabled</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shifter Status Flag interrupt enabled</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTEIEN</name>
|
|
<description>Shifter Error Interrupt Enable</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEIE</name>
|
|
<description>Shifter Error Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Shifter Error Flag interrupt disabled</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shifter Error Flag interrupt enabled</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMIEN</name>
|
|
<description>Timer Interrupt Enable Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Timer Status Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Timer Status Flag interrupt is disabled</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Timer Status Flag interrupt is enabled</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTSDEN</name>
|
|
<description>Shifter Status DMA Enable</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSDE</name>
|
|
<description>Shifter Status DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Shifter Status Flag DMA request is disabled</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shifter Status Flag DMA request is enabled</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTSTATE</name>
|
|
<description>Shifter State Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STATE</name>
|
|
<description>Current State Pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>SHIFTCTL%s</name>
|
|
<description>Shifter Control N Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMOD</name>
|
|
<description>Shifter Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Disabled.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>State mode. SHIFTBUF contents are used for storing programmable state attributes.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINPOL</name>
|
|
<description>Shifter Pin Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is active high</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is active low</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINSEL</name>
|
|
<description>Shifter Pin Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Shifter Pin Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Shifter pin output disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Shifter pin open drain or bidirectional output enable</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Shifter pin bidirectional output data</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Shifter pin output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMPOL</name>
|
|
<description>Timer Polarity</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Shift on posedge of Shift clock</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shift on negedge of Shift clock</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMSEL</name>
|
|
<description>Timer Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>SHIFTCFG%s</name>
|
|
<description>Shifter Configuration N Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SSTART</name>
|
|
<description>Shifter Start bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSTOP</name>
|
|
<description>Shifter Stop bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Stop bit disabled for transmitter/receiver/match store</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Reserved for transmitter/receiver/match store</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INSRC</name>
|
|
<description>Input Source</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Shifter N+1 Output</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>SHIFTBUF%s</name>
|
|
<description>Shifter Buffer N Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUF</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>SHIFTBUFBIS%s</name>
|
|
<description>Shifter Buffer N Bit Swapped Register</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFBIS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>SHIFTBUFBYS%s</name>
|
|
<description>Shifter Buffer N Byte Swapped Register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFBYS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>SHIFTBUFBBS%s</name>
|
|
<description>Shifter Buffer N Bit Byte Swapped Register</description>
|
|
<addressOffset>0x380</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SHIFTBUFBBS</name>
|
|
<description>Shift Buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TIMCTL%s</name>
|
|
<description>Timer Control N Register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TIMOD</name>
|
|
<description>Timer Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Timer Disabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Dual 8-bit counters baud/bit mode.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Dual 8-bit counters PWM mode.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Single 16-bit counter mode.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINPOL</name>
|
|
<description>Timer Pin Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is active high</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is active low</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINSEL</name>
|
|
<description>Timer Pin Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Timer Pin Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Timer pin output disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Timer pin open drain or bidirectional output enable</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Timer pin bidirectional output data</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Timer pin output</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSRC</name>
|
|
<description>Trigger Source</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External trigger selected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal trigger selected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGPOL</name>
|
|
<description>Trigger Polarity</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger active high</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger active low</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TIMCFG%s</name>
|
|
<description>Timer Configuration N Register</description>
|
|
<addressOffset>0x480</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TSTART</name>
|
|
<description>Timer Start Bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Start bit disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Start bit enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TSTOP</name>
|
|
<description>Timer Stop Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Stop bit disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Stop bit is enabled on timer compare</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Stop bit is enabled on timer disable</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Stop bit is enabled on timer compare and timer disable</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMENA</name>
|
|
<description>Timer Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Timer always enabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Timer enabled on Timer N-1 enable</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Timer enabled on Trigger high</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Timer enabled on Trigger high and Pin high</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Timer enabled on Pin rising edge</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Timer enabled on Pin rising edge and Trigger high</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Timer enabled on Trigger rising edge</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Timer enabled on Trigger rising or falling edge</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMDIS</name>
|
|
<description>Timer Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Timer never disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Timer disabled on Timer N-1 disable</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Timer disabled on Timer compare</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Timer disabled on Timer compare and Trigger Low</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Timer disabled on Pin rising or falling edge</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Timer disabled on Pin rising or falling edge provided Trigger is high</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Timer disabled on Trigger falling edge</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMRST</name>
|
|
<description>Timer Reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Timer never reset</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Timer reset on Timer Pin equal to Timer Output</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Timer reset on Timer Trigger equal to Timer Output</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Timer reset on Timer Pin rising edge</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Timer reset on Trigger rising edge</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Timer reset on Trigger rising or falling edge</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMDEC</name>
|
|
<description>Timer Decrement</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Decrement counter on FlexIO clock, Shift clock equals Timer output.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Decrement counter on Trigger input (both edges), Shift clock equals Timer output.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Decrement counter on Pin input (both edges), Shift clock equals Pin input.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMOUT</name>
|
|
<description>Timer Output</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Timer output is logic one when enabled and is not affected by timer reset</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Timer output is logic zero when enabled and is not affected by timer reset</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Timer output is logic one when enabled and on timer reset</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Timer output is logic zero when enabled and on timer reset</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>TIMCMP%s</name>
|
|
<description>Timer Compare N Register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CMP</name>
|
|
<description>Timer Compare Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OSC32</name>
|
|
<description>RTC Oscillator</description>
|
|
<prependToName>OSC32_</prependToName>
|
|
<baseAddress>0x40060000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>RTC Oscillator Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ROSCEREFS</name>
|
|
<description>RTC 32k Oscillator external reference clcok selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Bypass mode. RTC oscillator selects the external 32k clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Crystal mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSCSTB</name>
|
|
<description>RTC 32k Oscillator stable flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTC 32k oscillator is unstable now and no clock will go out of the block.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTC 32k oscillator is stable.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSCSTPEN</name>
|
|
<description>RTC 32k Oscillator stop mode enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Oscillator is disabled regardless the state of ROSCEN.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Oscillator is enabled in Stop mode when ROSCEN is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSCEN</name>
|
|
<description>RTC 32k Oscillator enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Oscillator is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Oscillator is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EWM</name>
|
|
<description>External Watchdog Monitor</description>
|
|
<prependToName>EWM_</prependToName>
|
|
<baseAddress>0x40061000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x6</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WDOG_EWM</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWMEN</name>
|
|
<description>EWM enable.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASSIN</name>
|
|
<description>EWM_in's Assertion State Select.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INEN</name>
|
|
<description>Input Enable.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INTEN</name>
|
|
<description>Interrupt Enable.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SERV</name>
|
|
<description>Service Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SERVICE</name>
|
|
<description>The EWM refresh mechanism requires the CPU to write two values to the SERV register: a first data byte of 0xB4, followed by a second data byte of 0x2C</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPL</name>
|
|
<description>Compare Low Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPAREL</name>
|
|
<description>To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) minimum refresh time is required</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMPH</name>
|
|
<description>Compare High Register</description>
|
|
<addressOffset>0x3</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPAREH</name>
|
|
<description>To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum refresh time is required</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKPRESCALER</name>
|
|
<description>Clock Prescaler Register</description>
|
|
<addressOffset>0x5</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLK_DIV</name>
|
|
<description>Selected low power clock source for running the EWM counter can be prescaled as below</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRGMUX0</name>
|
|
<description>TRGMUX</description>
|
|
<groupName>TRGMUX</groupName>
|
|
<baseAddress>0x40062000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x70</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TRGMUX_DMAMUX0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Trigger MUX Input 3 Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_EXTOUT0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Trigger MUX Input 3 Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_EXTOUT1</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Trigger MUX Input 3 Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_ADC0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_ADC1</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_CMP0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_CMP1</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_FTM0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Trigger MUX Input 3 Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_FTM1</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_FTM2</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_PDB0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_FLEXIO</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Trigger MUX Input 3 Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_LPIT0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Trigger MUX Input 3 Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_LPUART0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_LPUART1</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_LPI2C0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_LPI2C1</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_LPSPI0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_LPSPI1</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_LPTMR0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_TSI</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_PWT</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRGMUX1</name>
|
|
<description>TRGMUX</description>
|
|
<groupName>TRGMUX</groupName>
|
|
<baseAddress>0x40063000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x8</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TRGMUX_CTRL0</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Trigger MUX Input 3 Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRGMUX_CTRL1</name>
|
|
<description>TRGMUX Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Trigger MUX Input 0 Source Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Trigger MUX Input 1 Source Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Trigger MUX Input 2 Source Select</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Trigger MUX Input 3 Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Register cannot be written until the next system Reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SCG</name>
|
|
<description>System Clock Generator</description>
|
|
<prependToName>SCG_</prependToName>
|
|
<baseAddress>0x40064000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x518</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SCG</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VERSION</name>
|
|
<description>SCG Version Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xF80000FE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKPRES</name>
|
|
<description>Clock Present</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIVPRES</name>
|
|
<description>Divider Present</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>Clock Status Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x3000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVSLOW</name>
|
|
<description>Slow Clock Divide Ratio</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVCORE</name>
|
|
<description>Core Clock Divide Ratio</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Divide-by-1</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Divide-by-9</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Divide-by-10</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Divide-by-11</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Divide-by-12</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Divide-by-13</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Divide-by-14</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divide-by-15</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divide-by-16</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>System Clock Source</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>System OSC</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Slow IRC</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Fast IRC</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Low Power FLL (LPFLL)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCCR</name>
|
|
<description>Run Clock Control Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVSLOW</name>
|
|
<description>Slow Clock Divide Ratio</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVCORE</name>
|
|
<description>Core Clock Divide Ratio</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Divide-by-1</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Divide-by-9</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Divide-by-10</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Divide-by-11</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Divide-by-12</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Divide-by-13</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Divide-by-14</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divide-by-15</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divide-by-16</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>System Clock Source</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>System OSC</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Slow IRC</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Fast IRC</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Low Power FLL (LPFLL)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VCCR</name>
|
|
<description>VLPR Clock Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2000001</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVSLOW</name>
|
|
<description>Slow Clock Divide Ratio</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIVCORE</name>
|
|
<description>Core Clock Divide Ratio</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Divide-by-1</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>Divide-by-2</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Divide-by-3</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Divide-by-4</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Divide-by-5</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Divide-by-6</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Divide-by-7</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Divide-by-8</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1000</name>
|
|
<description>Divide-by-9</description>
|
|
<value>#1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1001</name>
|
|
<description>Divide-by-10</description>
|
|
<value>#1001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1010</name>
|
|
<description>Divide-by-11</description>
|
|
<value>#1010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1011</name>
|
|
<description>Divide-by-12</description>
|
|
<value>#1011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1100</name>
|
|
<description>Divide-by-13</description>
|
|
<value>#1100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1101</name>
|
|
<description>Divide-by-14</description>
|
|
<value>#1101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1110</name>
|
|
<description>Divide-by-15</description>
|
|
<value>#1110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1111</name>
|
|
<description>Divide-by-16</description>
|
|
<value>#1111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>System Clock Source</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>System OSC</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Slow IRC</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKOUTCNFG</name>
|
|
<description>SCG CLKOUT Configuration Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKOUTSEL</name>
|
|
<description>SCG Clkout Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>SCG SLOW Clock</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0001</name>
|
|
<description>System OSC</description>
|
|
<value>#0001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0010</name>
|
|
<description>Slow IRC</description>
|
|
<value>#0010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0011</name>
|
|
<description>Fast IRC</description>
|
|
<value>#0011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Low Power FLL (LPFLL)</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOSCCSR</name>
|
|
<description>System OSC Control Status Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOSCEN</name>
|
|
<description>System OSC Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System OSC is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System OSC is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCSTEN</name>
|
|
<description>System OSC Stop Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System OSC is disabled in Stop modes</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System OSC is enabled in Stop modes if SOSCEN=1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCLPEN</name>
|
|
<description>System OSC Low Power Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System OSC is disabled in VLP modes</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System OSC is enabled in VLP modes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCERCLKEN</name>
|
|
<description>System OSC 3V ERCLK Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System OSC 3V ERCLK output clock is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System OSC 3V ERCLK output clock is enabled when SYSOSC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCCM</name>
|
|
<description>System OSC Clock Monitor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System OSC Clock Monitor is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System OSC Clock Monitor is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCCMRE</name>
|
|
<description>System OSC Clock Monitor Reset Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock Monitor generates interrupt when error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock Monitor generates reset when error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>This Control Status Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>This Control Status Register cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCVLD</name>
|
|
<description>System OSC Valid</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System OSC is not enabled or clock is not valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System OSC is enabled and output clock is valid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCSEL</name>
|
|
<description>System OSC Selected</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System OSC is not the system clock source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System OSC is the system clock source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCERR</name>
|
|
<description>System OSC Clock Error</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>System OSC Clock Monitor is disabled or has not detected an error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>System OSC Clock Monitor is enabled and detected an error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOSCDIV</name>
|
|
<description>System OSC Divide Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SOSCDIV1</name>
|
|
<description>System OSC Clock Divide 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Output disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 16</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 32</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 64</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOSCDIV2</name>
|
|
<description>System OSC Clock Divide 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Output disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 16</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 32</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 64</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOSCCFG</name>
|
|
<description>System Oscillator Configuration Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EREFS</name>
|
|
<description>External Reference Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>External reference clock selected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Internal crystal oscillator of OSC requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HGO</name>
|
|
<description>High Gain Oscillator Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configure crystal oscillaor for low-power operation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configure crystal oscillator for high-gain operation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RANGE</name>
|
|
<description>System OSC Range Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Low frequency range selected for the crystal oscillator of 32 kHz to 40 kHz.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Medium frequency range selected for the crytstal oscillator of 1 Mhz to 8 Mhz.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>High frequency range selected for the crystal oscillator of 8 Mhz to 32 Mhz.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIRCCSR</name>
|
|
<description>Slow IRC Control Status Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000005</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIRCEN</name>
|
|
<description>Slow IRC Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slow IRC is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow IRC is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIRCSTEN</name>
|
|
<description>Slow IRC Stop Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slow IRC is disabled in Stop modes</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow IRC is enabled in Stop modes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIRCLPEN</name>
|
|
<description>Slow IRC Low Power Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slow IRC is disabled in VLP modes</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow IRC is enabled in VLP modes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Control Status Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Control Status Register cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIRCVLD</name>
|
|
<description>Slow IRC Valid</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slow IRC is not enabled or clock is not valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow IRC is enabled and output clock is valid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIRCSEL</name>
|
|
<description>Slow IRC Selected</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slow IRC is not the system clock source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow IRC is the system clock source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIRCDIV</name>
|
|
<description>Slow IRC Divide Register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SIRCDIV1</name>
|
|
<description>Slow IRC Clock Divide 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Output disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 16</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 32</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 64</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SIRCDIV2</name>
|
|
<description>Slow IRC Clock Divide 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Output disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 16</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 32</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 64</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIRCCFG</name>
|
|
<description>Slow IRC Configuration Register</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RANGE</name>
|
|
<description>Frequency Range</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slow IRC low range clock (2 MHz)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slow IRC high range clock (8 MHz )</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIRCCSR</name>
|
|
<description>Fast IRC Control Status Register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIRCEN</name>
|
|
<description>Fast IRC Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast IRC is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast IRC is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCSTEN</name>
|
|
<description>Fast IRC Stop Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast IRC is disabled in Stop modes. When selected as the reference clock to the System PLL and if the System PLL is enabled in STOP mode, the Fast IRC will stay enabled even if FIRCSTEN=0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast IRC is enabled in Stop modes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCLPEN</name>
|
|
<description>Fast IRC Low Power Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast IRC is disabled in VLP modes</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast IRC is enabled in VLP modes</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCREGOFF</name>
|
|
<description>Fast IRC Regulator Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast IRC Regulator is enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast IRC Regulator is disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCTREN</name>
|
|
<description>Fast IRC Trim Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable trimming Fast IRC to an external clock source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable trimming Fast IRC to an external clock source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCTRUP</name>
|
|
<description>Fast IRC Trim Update</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable Fast IRC trimming updates</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable Fast IRC trimming updates</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Control Status Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Control Status Register cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCVLD</name>
|
|
<description>Fast IRC Valid status</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast IRC is not enabled or clock is not valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast IRC is enabled and output clock is valid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCSEL</name>
|
|
<description>Fast IRC Selected status</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fast IRC is not the system clock source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fast IRC is the system clock source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCERR</name>
|
|
<description>Fast IRC Clock Error</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Error not detected with the Fast IRC trimming.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error detected with the Fast IRC trimming.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIRCDIV</name>
|
|
<description>Fast IRC Divide Register</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FIRCDIV1</name>
|
|
<description>Fast IRC Clock Divide 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Output disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 16</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 32</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 64</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FIRCDIV2</name>
|
|
<description>Fast IRC Clock Divide 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Output disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 16</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 32</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 64</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIRCCFG</name>
|
|
<description>Fast IRC Configuration Register</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RANGE</name>
|
|
<description>Frequency Range</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Fast IRC is trimmed to 48 MHz</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Fast IRC is trimmed to 52 MHz</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Fast IRC is trimmed to 56 MHz</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Fast IRC is trimmed to 60 MHz</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIRCTCFG</name>
|
|
<description>Fast IRC Trim Configuration Register</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIMSRC</name>
|
|
<description>Trim Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>System OSC</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIMDIV</name>
|
|
<description>Fast IRC Trim Predivide</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 128</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 256</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 512</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 1024</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 2048</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Reserved. Writing this value will result in Divide by 1.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Reserved. Writing this value will result in a Divide by 1.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIRCSTAT</name>
|
|
<description>Fast IRC Status Register</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIMFINE</name>
|
|
<description>Trim Fine Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIMCOAR</name>
|
|
<description>Trim Coarse</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ROSCCSR</name>
|
|
<description>RTC OSC Control Status Register</description>
|
|
<addressOffset>0x400</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ROSCCM</name>
|
|
<description>RTC OSC Clock Monitor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTC OSC Clock Monitor is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTC OSC Clock Monitor is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSCCMRE</name>
|
|
<description>RTC OSC Clock Monitor Reset Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock Monitor generates interrupt when error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock Monitor generates reset when error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Control Status Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Control Status Register cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSCVLD</name>
|
|
<description>RTC OSC Valid</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTC OSC is not enabled or clock is not valid</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTC OSC is enabled and output clock is valid</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ROSCERR</name>
|
|
<description>RTC OSC Clock Error</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RTC OSC Clock Monitor is disabled or has not detected an error</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPFLLCSR</name>
|
|
<description>Low Power FLL Control Status Register</description>
|
|
<addressOffset>0x500</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPFLLEN</name>
|
|
<description>LPFLL Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPFLL is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPFLL is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLTREN</name>
|
|
<description>LPFLL Trim Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable trimming LPFLL to an reference clock source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable trimming LPFLL to an reference clock source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLTRUP</name>
|
|
<description>LPFLL Trim Update</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLTRMLOCK</name>
|
|
<description>LPFLL Trim LOCK</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPFLL not Locked</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPFLL trimmed and Locked</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLCM</name>
|
|
<description>LPFLL Clock Monitor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPFLL Clock Monitor is disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPFLL Clock Monitor is enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLCMRE</name>
|
|
<description>LPFLL Clock Monitor Reset Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock Monitor generates interrupt when error detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock Monitor generates reset when error detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>Lock Register</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Control Status Register can be written.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Control Status Register cannot be written.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLVLD</name>
|
|
<description>LPFLL Valid</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPFLL is not enabled or clock is not valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPFLL is enabled and output clock is valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLSEL</name>
|
|
<description>LPFLL Selected</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPFLL is not the system clock source</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPFLL is the system clock source</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLERR</name>
|
|
<description>LPFLL Clock Error</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Error not detected with the LPFLL trimming.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Error detected with the LPFLL trimming.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPFLLDIV</name>
|
|
<description>Low Power FLL Divide Register</description>
|
|
<addressOffset>0x504</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPFLLDIV1</name>
|
|
<description>LPFLL Clock Divide 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Output disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 16</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 32</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 64</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPFLLDIV2</name>
|
|
<description>LPFLL Clock Divide 2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Output disabled</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 4</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 8</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 16</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 32</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 64</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPFLLCFG</name>
|
|
<description>Low Power FLL Configuration Register</description>
|
|
<addressOffset>0x508</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FSEL</name>
|
|
<description>Frequency Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>LPFLL is trimmed to 48 MHz</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>LPFLL is trimmed to 72 MHz</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPFLLTCFG</name>
|
|
<description>Low Power FLL Trim Configuration Register</description>
|
|
<addressOffset>0x50C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRIMSRC</name>
|
|
<description>Trim Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>SIRC</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>FIRC</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>System OSC</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>RTC OSC</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TRIMDIV</name>
|
|
<description>LPFLL Trim Predivide</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCKW2LSB</name>
|
|
<description>Lock LPFLL with 2 LSBS</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPFLL locks within 1LSB (0.4%)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPFLL locks within 2LSB (0.8%)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPFLLSTAT</name>
|
|
<description>Low Power FLL Status Register</description>
|
|
<addressOffset>0x514</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOTRIM</name>
|
|
<description>Auto Tune Trim Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PCC</name>
|
|
<description>PCC</description>
|
|
<baseAddress>0x40065000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x20</offset>
|
|
<size>0x1B4</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PCC_DMA0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_FLASH</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_DMAMUX0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_ADC1</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPSPI0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPSPI1</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_CRC</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_PDB0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPIT0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_FLEXTMR0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_FLEXTMR1</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_FLEXTMR2</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_ADC0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xEC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_RTC</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0xF4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCD</name>
|
|
<description>Peripheral Clock Divider Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Divide by 1 (pass-through, no clock divide).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Divide by 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>Divide by 3.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>Divide by 4.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4</name>
|
|
<description>Divide by 5.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5</name>
|
|
<description>Divide by 6.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>Divide by 7.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7</name>
|
|
<description>Divide by 8.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC</name>
|
|
<description>Peripheral Clock Divider Fraction</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fractional value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fractional value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPTMR0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCD</name>
|
|
<description>Peripheral Clock Divider Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Divide by 1 (pass-through, no clock divide).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Divide by 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>Divide by 3.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>Divide by 4.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>4</name>
|
|
<description>Divide by 5.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>5</name>
|
|
<description>Divide by 6.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>Divide by 7.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>7</name>
|
|
<description>Divide by 8.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRAC</name>
|
|
<description>Peripheral Clock Divider Fraction</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fractional value is 0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Fractional value is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_TSI</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_PORTA</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_PORTB</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_PORTC</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_PORTD</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_PORTE</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_PWT</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_FLEXIO</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_OSC32</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_EWM</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPI2C0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPI2C1</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPUART0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPUART1</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_LPUART2</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Peripheral Clock Source Select</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Clock is off (or test clock is enabled).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>OSCCLK - System Oscillator Bus Clock(scg_sosc_slow_clk).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>2</name>
|
|
<description>SCGIRCLK - Slow IRC Clock(scg_sirc_slow_clk), (maximum is 8MHz).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>3</name>
|
|
<description>SCGFIRCLK - Fast IRC Clock(scg_firc_slow_clk), (maximum is 48MHz).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>6</name>
|
|
<description>SCGPCLK System PLL clock(scg_spll_slow_clk).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_CMP0</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCC_CMP1</name>
|
|
<description>PCC Register</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>INUSE</name>
|
|
<description>Clock Gate Control</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not being used.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is being used. Software cannot modify the existing clocking configuration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CGC</name>
|
|
<description>Clock Control</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Peripheral is not present.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Peripheral is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPI2C0</name>
|
|
<description>The LPI2C Memory Map/Register Definition can be found here.</description>
|
|
<groupName>LPI2C</groupName>
|
|
<prependToName>LPI2C0_</prependToName>
|
|
<baseAddress>0x40066000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x174</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPI2C0</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Specification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Master only with standard feature set.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Master and slave with standard feature set.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTXFIFO</name>
|
|
<description>Master Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MRXFIFO</name>
|
|
<description>Master Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Master Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>Master Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master logic is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master logic is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master logic is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master logic is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEN</name>
|
|
<description>Doze mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master is enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master is disabled in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master is enabled in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Master Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive Data is not ready.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is ready.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPF</name>
|
|
<description>End Packet Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master has not generated a STOP or Repeated START condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master has generated a STOP or Repeated START condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDF</name>
|
|
<description>STOP Detect Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master has not generated a STOP condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master has generated a STOP condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDF</name>
|
|
<description>NACK Detect Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Unexpected NACK not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Unexpected NACK was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALF</name>
|
|
<description>Arbitration Lost Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master has not lost arbitration.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master has lost arbitration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master sending or receiving data without START condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLTF</name>
|
|
<description>Pin Low Timeout Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin low timeout has not occurred or is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin low timeout has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMF</name>
|
|
<description>Data Match Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Have not received matching data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Have received matching data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBF</name>
|
|
<description>Master Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C Master is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C Master is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BBF</name>
|
|
<description>Bus Busy Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C Bus is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C Bus is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIER</name>
|
|
<description>Master Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPIE</name>
|
|
<description>End Packet Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIE</name>
|
|
<description>STOP Detect Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDIE</name>
|
|
<description>NACK Detect Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALIE</name>
|
|
<description>Arbitration Lost Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLTIE</name>
|
|
<description>Pin Low Timeout Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMIE</name>
|
|
<description>Data Match Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDER</name>
|
|
<description>Master DMA Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR0</name>
|
|
<description>Master Configuration Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HREN</name>
|
|
<description>Host Request Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host request input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host request input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRPOL</name>
|
|
<description>Host Request Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRSEL</name>
|
|
<description>Host Request Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host request input is pin LPI2C_HREQ.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host request input is input trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIRFIFO</name>
|
|
<description>Circular FIFO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Circular FIFO is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Circular FIFO is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMO</name>
|
|
<description>Receive Data Match Only</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is stored in the receive FIFO as normal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is discarded unless the RMF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR1</name>
|
|
<description>Master Configuration Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSTOP</name>
|
|
<description>Automatic STOP Generation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IGNACK</name>
|
|
<description>When set, the received NACK field is ignored and assumed to be ACK</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPI2C Master will receive ACK and NACK normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPI2C Master will treat a received NACK as if it was an ACK.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMECFG</name>
|
|
<description>Timeout Configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Match disabled.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Match enabled (1st data word equals MATCH0 OR MATCH1).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Match enabled (any data word equals MATCH0 OR MATCH1).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Match enabled (any data word equals MATCH0 AND next data word equals MATCH1).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Pin Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>LPI2C configured for 2-pin open drain mode.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>LPI2C configured for 2-pin output only mode (ultra-fast mode).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>LPI2C configured for 2-pin push-pull mode.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>LPI2C configured for 4-pin push-pull mode.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>LPI2C configured for 2-pin open drain mode with separate LPI2C slave.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>LPI2C configured for 2-pin push-pull mode with separate LPI2C slave.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>LPI2C configured for 4-pin push-pull mode (inverted outputs).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR2</name>
|
|
<description>Master Configuration Register 2</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSIDLE</name>
|
|
<description>Bus Idle Timeout</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSCL</name>
|
|
<description>Glitch Filter SCL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSDA</name>
|
|
<description>Glitch Filter SDA</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR3</name>
|
|
<description>Master Configuration Register 3</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOW</name>
|
|
<description>Pin Low Timeout</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMR</name>
|
|
<description>Master Data Match Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH0</name>
|
|
<description>Match 0 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCH1</name>
|
|
<description>Match 1 Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCCR0</name>
|
|
<description>Master Clock Configuration Register 0</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKLO</name>
|
|
<description>Clock Low Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKHI</name>
|
|
<description>Clock High Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETHOLD</name>
|
|
<description>Setup Hold Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCCR1</name>
|
|
<description>Master Clock Configuration Register 1</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKLO</name>
|
|
<description>Clock Low Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKHI</name>
|
|
<description>Clock High Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETHOLD</name>
|
|
<description>Setup Hold Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MFCR</name>
|
|
<description>Master FIFO Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit FIFO Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive FIFO Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MFSR</name>
|
|
<description>Master FIFO Status Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit FIFO Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive FIFO Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MTDR</name>
|
|
<description>Master Transmit Data Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit DATA[7:0].</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive (DATA[7:0] + 1) bytes.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Generate STOP condition.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive and discard (DATA[7:0] + 1) bytes.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0].</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0] using high speed mode.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRDR</name>
|
|
<description>Master Receive Data Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX Empty</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Slave Control Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEN</name>
|
|
<description>Slave Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave logic is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave logic is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN</name>
|
|
<description>Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable digital filter and output delay counter for slave mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable digital filter and output delay counter for slave mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTDZ</name>
|
|
<description>Filter Doze Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Filter remains enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Filter is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit Data Register is now empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive Data Register is now empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSR</name>
|
|
<description>Slave Status Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive Data is not ready.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is ready.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVF</name>
|
|
<description>Address Valid Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Address Status Register is not valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address Status Register is valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAF</name>
|
|
<description>Transmit ACK Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit ACK/NACK is not required.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit ACK/NACK is required.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSF</name>
|
|
<description>Repeated Start Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave has not detected a Repeated START condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave has detected a Repeated START condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDF</name>
|
|
<description>STOP Detect Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave has not detected a STOP condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave has detected a STOP condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEF</name>
|
|
<description>Bit Error Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave has not detected a bit error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave has detected a bit error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO underflow or overflow not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO underflow or overflow detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM0F</name>
|
|
<description>Address Match 0 Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Have not received ADDR0 matching address.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Have received ADDR0 matching address.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM1F</name>
|
|
<description>Address Match 1 Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Have not received ADDR1 or ADDR0/ADDR1 range matching address.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Have received ADDR1 or ADDR0/ADDR1 range matching address.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCF</name>
|
|
<description>General Call Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave has not detected the General Call Address or General Call Address disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave has detected the General Call Address.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARF</name>
|
|
<description>SMBus Alert Response Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SMBus Alert Response disabled or not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SMBus Alert Response enabled and detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBF</name>
|
|
<description>Slave Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C Slave is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C Slave is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BBF</name>
|
|
<description>Bus Busy Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C Bus is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C Bus is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIER</name>
|
|
<description>Slave Interrupt Enable Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVIE</name>
|
|
<description>Address Valid Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>Transmit ACK Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSIE</name>
|
|
<description>Repeated Start Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIE</name>
|
|
<description>STOP Detect Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEIE</name>
|
|
<description>Bit Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM0IE</name>
|
|
<description>Address Match 0 Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM1F</name>
|
|
<description>Address Match 1 Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCIE</name>
|
|
<description>General Call Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARIE</name>
|
|
<description>SMBus Alert Response Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDER</name>
|
|
<description>Slave DMA Enable Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVDE</name>
|
|
<description>Address Valid DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGR1</name>
|
|
<description>Slave Configuration Register 1</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRSTALL</name>
|
|
<description>Address SCL Stall</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock stretching disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock stretching enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXSTALL</name>
|
|
<description>RX SCL Stall</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock stretching disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock stretching enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDSTALL</name>
|
|
<description>TX Data SCL Stall</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock stretching disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock stretching enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKSTALL</name>
|
|
<description>ACK SCL Stall</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock stretching disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock stretching enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>General Call Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>General Call address is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>General call address is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAEN</name>
|
|
<description>SMBus Alert Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables match on SMBus Alert.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables match on SMBus Alert.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCFG</name>
|
|
<description>Transmit Flag Configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit Data Flag will assert whenever the transmit data register is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXCFG</name>
|
|
<description>Receive Data Configuration</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reading the receive data register will return receive data and clear the receive data flag.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag. Reading the receive data register when the address valid flag is clear will return receive data and clear the receive data flag.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IGNACK</name>
|
|
<description>Ignore NACK</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave will end transfer when NACK detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave will not end transfer when NACK detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSMEN</name>
|
|
<description>High Speed Mode Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables detection of Hs-mode master code.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables detection of Hs-mode master code.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDRCFG</name>
|
|
<description>Address Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Address match 0 (7-bit).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Address match 0 (10-bit).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Address match 0 (7-bit) or Address match 1 (7-bit).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Address match 0 (10-bit) or Address match 1 (10-bit).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Address match 0 (7-bit) or Address match 1 (10-bit).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Address match 0 (10-bit) or Address match 1 (7-bit).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>From Address match 0 (7-bit) to Address match 1 (7-bit).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>From Address match 0 (10-bit) to Address match 1 (10-bit).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGR2</name>
|
|
<description>Slave Configuration Register 2</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKHOLD</name>
|
|
<description>Clock Hold Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSCL</name>
|
|
<description>Glitch Filter SCL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSDA</name>
|
|
<description>Glitch Filter SDA</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAMR</name>
|
|
<description>Slave Address Match Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR0</name>
|
|
<description>Address 0 Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR1</name>
|
|
<description>Address 1 Value</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SASR</name>
|
|
<description>Slave Address Status Register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RADDR</name>
|
|
<description>Received Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ANV</name>
|
|
<description>Address Not Valid</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RADDR is valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RADDR is not valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAR</name>
|
|
<description>Slave Transmit ACK Register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXNACK</name>
|
|
<description>Transmit NACK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit ACK for received word.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit NACK for received word.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STDR</name>
|
|
<description>Slave Transmit Data Register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRDR</name>
|
|
<description>Slave Receive Data Register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX Empty</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The Receive Data Register is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The Receive Data Register is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates this is not the first data word since a (repeated) START or STOP condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates this is the first data word since a (repeated) START or STOP condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPI2C1</name>
|
|
<description>The LPI2C Memory Map/Register Definition can be found here.</description>
|
|
<groupName>LPI2C</groupName>
|
|
<prependToName>LPI2C1_</prependToName>
|
|
<baseAddress>0x40067000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x174</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPI2C1</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Specification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Master only with standard feature set.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Master and slave with standard feature set.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MTXFIFO</name>
|
|
<description>Master Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MRXFIFO</name>
|
|
<description>Master Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>Master Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MEN</name>
|
|
<description>Master Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master logic is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master logic is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master logic is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master logic is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEN</name>
|
|
<description>Doze mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master is enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master is disabled in debug mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master is enabled in debug mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSR</name>
|
|
<description>Master Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive Data is not ready.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is ready.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPF</name>
|
|
<description>End Packet Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master has not generated a STOP or Repeated START condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master has generated a STOP or Repeated START condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDF</name>
|
|
<description>STOP Detect Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master has not generated a STOP condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master has generated a STOP condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDF</name>
|
|
<description>NACK Detect Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Unexpected NACK not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Unexpected NACK was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALF</name>
|
|
<description>Arbitration Lost Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Master has not lost arbitration.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master has lost arbitration.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Master sending or receiving data without START condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLTF</name>
|
|
<description>Pin Low Timeout Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin low timeout has not occurred or is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin low timeout has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMF</name>
|
|
<description>Data Match Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Have not received matching data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Have received matching data.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MBF</name>
|
|
<description>Master Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C Master is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C Master is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BBF</name>
|
|
<description>Bus Busy Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C Bus is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C Bus is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIER</name>
|
|
<description>Master Interrupt Enable Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPIE</name>
|
|
<description>End Packet Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIE</name>
|
|
<description>STOP Detect Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NDIE</name>
|
|
<description>NACK Detect Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ALIE</name>
|
|
<description>Arbitration Lost Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PLTIE</name>
|
|
<description>Pin Low Timeout Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMIE</name>
|
|
<description>Data Match Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDER</name>
|
|
<description>Master DMA Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR0</name>
|
|
<description>Master Configuration Register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HREN</name>
|
|
<description>Host Request Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host request input is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host request input is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRPOL</name>
|
|
<description>Host Request Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HRSEL</name>
|
|
<description>Host Request Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Host request input is pin LPI2C_HREQ.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Host request input is input trigger.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CIRFIFO</name>
|
|
<description>Circular FIFO Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Circular FIFO is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Circular FIFO is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMO</name>
|
|
<description>Receive Data Match Only</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is stored in the receive FIFO as normal.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is discarded unless the RMF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR1</name>
|
|
<description>Master Configuration Register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALE</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Divide by 1.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Divide by 2.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Divide by 4.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Divide by 8.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Divide by 16.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Divide by 32.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Divide by 64.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Divide by 128.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AUTOSTOP</name>
|
|
<description>Automatic STOP Generation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>STOP condition is automatically generated whenever the transmit FIFO is empty and LPI2C master is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IGNACK</name>
|
|
<description>When set, the received NACK field is ignored and assumed to be ACK</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPI2C Master will receive ACK and NACK normally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPI2C Master will treat a received NACK as if it was an ACK.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMECFG</name>
|
|
<description>Timeout Configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Match disabled.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Match enabled (1st data word equals MATCH0 OR MATCH1).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Match enabled (any data word equals MATCH0 OR MATCH1).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Match enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Match enabled (any data word equals MATCH0 AND next data word equals MATCH1).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Match enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Match enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PINCFG</name>
|
|
<description>Pin Configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>LPI2C configured for 2-pin open drain mode.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>LPI2C configured for 2-pin output only mode (ultra-fast mode).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>LPI2C configured for 2-pin push-pull mode.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>LPI2C configured for 4-pin push-pull mode.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>LPI2C configured for 2-pin open drain mode with separate LPI2C slave.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>LPI2C configured for 2-pin output only mode (ultra-fast mode) with separate LPI2C slave.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>LPI2C configured for 2-pin push-pull mode with separate LPI2C slave.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>LPI2C configured for 4-pin push-pull mode (inverted outputs).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR2</name>
|
|
<description>Master Configuration Register 2</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BUSIDLE</name>
|
|
<description>Bus Idle Timeout</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSCL</name>
|
|
<description>Glitch Filter SCL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSDA</name>
|
|
<description>Glitch Filter SDA</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCFGR3</name>
|
|
<description>Master Configuration Register 3</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PINLOW</name>
|
|
<description>Pin Low Timeout</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDMR</name>
|
|
<description>Master Data Match Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH0</name>
|
|
<description>Match 0 Value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCH1</name>
|
|
<description>Match 1 Value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCCR0</name>
|
|
<description>Master Clock Configuration Register 0</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKLO</name>
|
|
<description>Clock Low Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKHI</name>
|
|
<description>Clock High Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETHOLD</name>
|
|
<description>Setup Hold Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCCR1</name>
|
|
<description>Master Clock Configuration Register 1</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKLO</name>
|
|
<description>Clock Low Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKHI</name>
|
|
<description>Clock High Period</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SETHOLD</name>
|
|
<description>Setup Hold Delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MFCR</name>
|
|
<description>Master FIFO Control Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit FIFO Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive FIFO Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MFSR</name>
|
|
<description>Master FIFO Status Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit FIFO Count</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive FIFO Count</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MTDR</name>
|
|
<description>Master Transmit Data Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command Data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit DATA[7:0].</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive (DATA[7:0] + 1) bytes.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Generate STOP condition.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive and discard (DATA[7:0] + 1) bytes.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0].</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0] using high speed mode.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRDR</name>
|
|
<description>Master Receive Data Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX Empty</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<description>Slave Control Register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SEN</name>
|
|
<description>Slave Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave mode is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave mode is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave logic is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave logic is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTEN</name>
|
|
<description>Filter Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable digital filter and output delay counter for slave mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable digital filter and output delay counter for slave mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTDZ</name>
|
|
<description>Filter Doze Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Filter remains enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Filter is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Reset Transmit FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit Data Register is now empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRF</name>
|
|
<description>Reset Receive FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive Data Register is now empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSR</name>
|
|
<description>Slave Status Register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDF</name>
|
|
<description>Transmit Data Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not requested.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data is requested.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDF</name>
|
|
<description>Receive Data Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive Data is not ready.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data is ready.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVF</name>
|
|
<description>Address Valid Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Address Status Register is not valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Address Status Register is valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAF</name>
|
|
<description>Transmit ACK Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit ACK/NACK is not required.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit ACK/NACK is required.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSF</name>
|
|
<description>Repeated Start Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave has not detected a Repeated START condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave has detected a Repeated START condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDF</name>
|
|
<description>STOP Detect Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave has not detected a STOP condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave has detected a STOP condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEF</name>
|
|
<description>Bit Error Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave has not detected a bit error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave has detected a bit error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FIFO underflow or overflow not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>FIFO underflow or overflow detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM0F</name>
|
|
<description>Address Match 0 Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Have not received ADDR0 matching address.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Have received ADDR0 matching address.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM1F</name>
|
|
<description>Address Match 1 Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Have not received ADDR1 or ADDR0/ADDR1 range matching address.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Have received ADDR1 or ADDR0/ADDR1 range matching address.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCF</name>
|
|
<description>General Call Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave has not detected the General Call Address or General Call Address disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave has detected the General Call Address.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARF</name>
|
|
<description>SMBus Alert Response Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>SMBus Alert Response disabled or not detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>SMBus Alert Response enabled and detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBF</name>
|
|
<description>Slave Busy Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C Slave is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C Slave is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BBF</name>
|
|
<description>Bus Busy Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>I2C Bus is idle.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>I2C Bus is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIER</name>
|
|
<description>Slave Interrupt Enable Register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDIE</name>
|
|
<description>Transmit Data Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDIE</name>
|
|
<description>Receive Data Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVIE</name>
|
|
<description>Address Valid Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TAIE</name>
|
|
<description>Transmit ACK Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSIE</name>
|
|
<description>Repeated Start Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SDIE</name>
|
|
<description>STOP Detect Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BEIE</name>
|
|
<description>Bit Error Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM0IE</name>
|
|
<description>Address Match 0 Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AM1F</name>
|
|
<description>Address Match 1 Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCIE</name>
|
|
<description>General Call Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SARIE</name>
|
|
<description>SMBus Alert Response Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDER</name>
|
|
<description>Slave DMA Enable Register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TDDE</name>
|
|
<description>Transmit Data DMA Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDDE</name>
|
|
<description>Receive Data DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>AVDE</name>
|
|
<description>Address Valid DMA Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGR1</name>
|
|
<description>Slave Configuration Register 1</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADRSTALL</name>
|
|
<description>Address SCL Stall</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock stretching disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock stretching enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXSTALL</name>
|
|
<description>RX SCL Stall</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock stretching disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock stretching enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDSTALL</name>
|
|
<description>TX Data SCL Stall</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock stretching disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock stretching enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACKSTALL</name>
|
|
<description>ACK SCL Stall</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Clock stretching disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Clock stretching enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>General Call Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>General Call address is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>General call address is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SAEN</name>
|
|
<description>SMBus Alert Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables match on SMBus Alert.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables match on SMBus Alert.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCFG</name>
|
|
<description>Transmit Flag Configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit Data Flag will assert whenever the transmit data register is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXCFG</name>
|
|
<description>Receive Data Configuration</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reading the receive data register will return receive data and clear the receive data flag.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reading the receive data register when the address valid flag is set will return the address status register and clear the address valid flag. Reading the receive data register when the address valid flag is clear will return receive data and clear the receive data flag.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IGNACK</name>
|
|
<description>Ignore NACK</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Slave will end transfer when NACK detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Slave will not end transfer when NACK detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>HSMEN</name>
|
|
<description>High Speed Mode Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disables detection of Hs-mode master code.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables detection of Hs-mode master code.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADDRCFG</name>
|
|
<description>Address Configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Address match 0 (7-bit).</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Address match 0 (10-bit).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Address match 0 (7-bit) or Address match 1 (7-bit).</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Address match 0 (10-bit) or Address match 1 (10-bit).</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Address match 0 (7-bit) or Address match 1 (10-bit).</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Address match 0 (10-bit) or Address match 1 (7-bit).</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>From Address match 0 (7-bit) to Address match 1 (7-bit).</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>From Address match 0 (10-bit) to Address match 1 (10-bit).</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCFGR2</name>
|
|
<description>Slave Configuration Register 2</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CLKHOLD</name>
|
|
<description>Clock Hold Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATAVD</name>
|
|
<description>Data Valid Delay</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSCL</name>
|
|
<description>Glitch Filter SCL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FILTSDA</name>
|
|
<description>Glitch Filter SDA</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAMR</name>
|
|
<description>Slave Address Match Register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR0</name>
|
|
<description>Address 0 Value</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR1</name>
|
|
<description>Address 1 Value</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SASR</name>
|
|
<description>Slave Address Status Register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RADDR</name>
|
|
<description>Received Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ANV</name>
|
|
<description>Address Not Valid</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RADDR is valid.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RADDR is not valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAR</name>
|
|
<description>Slave Transmit ACK Register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXNACK</name>
|
|
<description>Transmit NACK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit ACK for received word.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit NACK for received word.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STDR</name>
|
|
<description>Slave Transmit Data Register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRDR</name>
|
|
<description>Slave Receive Data Register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Receive Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPTY</name>
|
|
<description>RX Empty</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The Receive Data Register is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The Receive Data Register is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start Of Frame</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Indicates this is not the first data word since a (repeated) START or STOP condition.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Indicates this is the first data word since a (repeated) START or STOP condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPUART0</name>
|
|
<description>LPUART</description>
|
|
<groupName>LPUART</groupName>
|
|
<baseAddress>0x4006A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPUART0</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4010003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Identification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x1</name>
|
|
<description>Standard feature set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x3</name>
|
|
<description>Standard feature set with MODEM/IrDA support.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GLOBAL</name>
|
|
<description>LPUART Global Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINCFG</name>
|
|
<description>LPUART Pin Configuration Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Input trigger is disabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Input trigger is used instead of RXD pin input.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Input trigger is used instead of CTS_B pin input.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Input trigger is used to modulate the TXD pin output.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>LPUART Baud Rate Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF000004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBNS</name>
|
|
<description>Stop Bit Number Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One stop bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Two stop bits.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RX Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESYNCDIS</name>
|
|
<description>Resynchronization Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Resynchronization during received data word is supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resynchronization during received data word is disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOTHEDGE</name>
|
|
<description>Both Edge Sampling</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver samples input data using the rising edge of the baud rate clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Address Match Wakeup</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Idle Match Wakeup</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Match On and Match Off</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIDMAE</name>
|
|
<description>Receiver Idle DMA Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMAE</name>
|
|
<description>Receiver Full DMA Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAE</name>
|
|
<description>Transmitter DMA Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSR</name>
|
|
<description>Oversampling Ratio</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 7-bit to 9-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 10-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables automatic address matching or data matching mode for MATCH[MA2].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables automatic address matching or data matching mode for MATCH[MA1].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>LPUART Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA2F</name>
|
|
<description>Match 2 Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is not equal to MA2</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is equal to MA2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA1F</name>
|
|
<description>Match 1 Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is not equal to MA1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is equal to MA1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected. This does not guarantee the framing is correct.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Noise detected in the received character in LPUART_DATA.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun (new LPUART data lost).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No idle line detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle line was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data buffer empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data buffer full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data buffer full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data buffer empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPUART receiver idle waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART receiver active (RXD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LIN break detect is disabled, normal break character can be detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Character Generation Length</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is transmitted with length of 9 to 13 bit times.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is transmitted with length of 12 to 15 bit times.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wake Up Idle Detect</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>MSB First</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RXD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>LPUART Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No hardware parity generation or checking.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures RWU for idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures RWU with address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-Bit or 8-Bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 8-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 9-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPUART is enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation - RXD and TXD use separate pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECFG</name>
|
|
<description>Idle Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 idle character</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 idle characters</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>4 idle characters</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>8 idle characters</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>16 idle characters</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>32 idle characters</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>64 idle characters</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>128 idle characters</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7</name>
|
|
<description>7-Bit Mode Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 8-bit to 10-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 7-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA2IE</name>
|
|
<description>Match 2 Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MA2F interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MA2F interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA1IE</name>
|
|
<description>Match 1 Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MA1F interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MA1F interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal receiver operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART receiver in standby waiting for wakeup condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from IDLE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when IDLE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RDRF disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when RDRF flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable for</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TC disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TC flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TDRE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TDRE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when PF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when FE is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when NF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when OR is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>TXD Pin Direction in Single-Wire Mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>R9T8</name>
|
|
<description>Receive Bit 9 / Transmit Bit 8</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T9</name>
|
|
<description>Receive Bit 8 / Transmit Bit 9</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>LPUART Data Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R0T0</name>
|
|
<description>R0T0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R1T1</name>
|
|
<description>R1T1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R2T2</name>
|
|
<description>R2T2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R3T3</name>
|
|
<description>R3T3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R4T4</name>
|
|
<description>R4T4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R5T5</name>
|
|
<description>R5T5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R6T6</name>
|
|
<description>R6T6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R7T7</name>
|
|
<description>R7T7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T8</name>
|
|
<description>R8T8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R9T9</name>
|
|
<description>R9T9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDLINE</name>
|
|
<description>Idle Line</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver was not idle before receiving this character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver was idle before receiving this character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer Empty</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer contains valid data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty, data returned on read is not valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRETSC</name>
|
|
<description>Frame Error / Transmit Special Character</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a frame error on read, transmit a normal character on write.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a frame error, transmit an idle or break character on transmit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>PARITYE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>NOISY</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATCH</name>
|
|
<description>LPUART Match Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA1</name>
|
|
<description>Match Address 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MA2</name>
|
|
<description>Match Address 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODIR</name>
|
|
<description>LPUART Modem IrDA Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSC</name>
|
|
<description>Transmit CTS Configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS input is sampled at the start of each character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CTS input is sampled when the transmitter is idle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSSRC</name>
|
|
<description>Transmit CTS Source</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS input is the CTS_B pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CTS input is the inverted Receiver Match result.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSWATER</name>
|
|
<description>Receive RTS Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1/OSR.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2/OSR.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3/OSR.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4/OSR.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO</name>
|
|
<description>LPUART FIFO Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00011</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Receive FIFO/Buffer depth = 256 datawords.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Transmit FIFO/Buffer depth = 256 datawords</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIDEN</name>
|
|
<description>Receiver Idle Empty Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Disable RDRF assertion due to partially filled FIFO when receiver is idle.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WATER</name>
|
|
<description>LPUART Watermark Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPUART1</name>
|
|
<description>LPUART</description>
|
|
<groupName>LPUART</groupName>
|
|
<baseAddress>0x4006B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPUART1</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4010003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Identification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x1</name>
|
|
<description>Standard feature set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x3</name>
|
|
<description>Standard feature set with MODEM/IrDA support.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GLOBAL</name>
|
|
<description>LPUART Global Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINCFG</name>
|
|
<description>LPUART Pin Configuration Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Input trigger is disabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Input trigger is used instead of RXD pin input.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Input trigger is used instead of CTS_B pin input.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Input trigger is used to modulate the TXD pin output.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>LPUART Baud Rate Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF000004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBNS</name>
|
|
<description>Stop Bit Number Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One stop bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Two stop bits.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RX Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESYNCDIS</name>
|
|
<description>Resynchronization Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Resynchronization during received data word is supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resynchronization during received data word is disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOTHEDGE</name>
|
|
<description>Both Edge Sampling</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver samples input data using the rising edge of the baud rate clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Address Match Wakeup</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Idle Match Wakeup</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Match On and Match Off</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIDMAE</name>
|
|
<description>Receiver Idle DMA Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMAE</name>
|
|
<description>Receiver Full DMA Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAE</name>
|
|
<description>Transmitter DMA Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSR</name>
|
|
<description>Oversampling Ratio</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 7-bit to 9-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 10-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables automatic address matching or data matching mode for MATCH[MA2].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables automatic address matching or data matching mode for MATCH[MA1].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>LPUART Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA2F</name>
|
|
<description>Match 2 Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is not equal to MA2</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is equal to MA2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA1F</name>
|
|
<description>Match 1 Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is not equal to MA1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is equal to MA1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected. This does not guarantee the framing is correct.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Noise detected in the received character in LPUART_DATA.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun (new LPUART data lost).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No idle line detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle line was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data buffer empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data buffer full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data buffer full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data buffer empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPUART receiver idle waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART receiver active (RXD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LIN break detect is disabled, normal break character can be detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Character Generation Length</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is transmitted with length of 9 to 13 bit times.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is transmitted with length of 12 to 15 bit times.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wake Up Idle Detect</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>MSB First</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RXD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>LPUART Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No hardware parity generation or checking.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures RWU for idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures RWU with address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-Bit or 8-Bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 8-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 9-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPUART is enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation - RXD and TXD use separate pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECFG</name>
|
|
<description>Idle Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 idle character</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 idle characters</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>4 idle characters</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>8 idle characters</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>16 idle characters</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>32 idle characters</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>64 idle characters</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>128 idle characters</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7</name>
|
|
<description>7-Bit Mode Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 8-bit to 10-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 7-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA2IE</name>
|
|
<description>Match 2 Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MA2F interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MA2F interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA1IE</name>
|
|
<description>Match 1 Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MA1F interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MA1F interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal receiver operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART receiver in standby waiting for wakeup condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from IDLE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when IDLE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RDRF disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when RDRF flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable for</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TC disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TC flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TDRE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TDRE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when PF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when FE is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when NF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when OR is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>TXD Pin Direction in Single-Wire Mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>R9T8</name>
|
|
<description>Receive Bit 9 / Transmit Bit 8</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T9</name>
|
|
<description>Receive Bit 8 / Transmit Bit 9</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>LPUART Data Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R0T0</name>
|
|
<description>R0T0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R1T1</name>
|
|
<description>R1T1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R2T2</name>
|
|
<description>R2T2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R3T3</name>
|
|
<description>R3T3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R4T4</name>
|
|
<description>R4T4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R5T5</name>
|
|
<description>R5T5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R6T6</name>
|
|
<description>R6T6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R7T7</name>
|
|
<description>R7T7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T8</name>
|
|
<description>R8T8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R9T9</name>
|
|
<description>R9T9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDLINE</name>
|
|
<description>Idle Line</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver was not idle before receiving this character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver was idle before receiving this character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer Empty</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer contains valid data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty, data returned on read is not valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRETSC</name>
|
|
<description>Frame Error / Transmit Special Character</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a frame error on read, transmit a normal character on write.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a frame error, transmit an idle or break character on transmit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>PARITYE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>NOISY</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATCH</name>
|
|
<description>LPUART Match Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA1</name>
|
|
<description>Match Address 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MA2</name>
|
|
<description>Match Address 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODIR</name>
|
|
<description>LPUART Modem IrDA Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSC</name>
|
|
<description>Transmit CTS Configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS input is sampled at the start of each character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CTS input is sampled when the transmitter is idle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSSRC</name>
|
|
<description>Transmit CTS Source</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS input is the CTS_B pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CTS input is the inverted Receiver Match result.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSWATER</name>
|
|
<description>Receive RTS Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1/OSR.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2/OSR.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3/OSR.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4/OSR.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO</name>
|
|
<description>LPUART FIFO Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00011</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Receive FIFO/Buffer depth = 256 datawords.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Transmit FIFO/Buffer depth = 256 datawords</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIDEN</name>
|
|
<description>Receiver Idle Empty Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Disable RDRF assertion due to partially filled FIFO when receiver is idle.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WATER</name>
|
|
<description>LPUART Watermark Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPUART2</name>
|
|
<description>LPUART</description>
|
|
<groupName>LPUART</groupName>
|
|
<baseAddress>0x4006C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPUART2</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4010003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Identification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0x1</name>
|
|
<description>Standard feature set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0x3</name>
|
|
<description>Standard feature set with MODEM/IrDA support.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x202</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXFIFO</name>
|
|
<description>Transmit FIFO Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFIFO</name>
|
|
<description>Receive FIFO Size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GLOBAL</name>
|
|
<description>LPUART Global Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Software Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Module is not reset.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Module is reset.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PINCFG</name>
|
|
<description>LPUART Pin Configuration Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TRGSEL</name>
|
|
<description>Trigger Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Input trigger is disabled.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Input trigger is used instead of RXD pin input.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Input trigger is used instead of CTS_B pin input.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Input trigger is used to modulate the TXD pin output.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<description>LPUART Baud Rate Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF000004</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SBR</name>
|
|
<description>Baud Rate Modulo Divisor.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SBNS</name>
|
|
<description>Stop Bit Number Select</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>One stop bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Two stop bits.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIE</name>
|
|
<description>RX Input Active Edge Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIE</name>
|
|
<description>LIN Break Detect Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RESYNCDIS</name>
|
|
<description>Resynchronization Disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Resynchronization during received data word is supported</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Resynchronization during received data word is disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BOTHEDGE</name>
|
|
<description>Both Edge Sampling</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver samples input data using the rising edge of the baud rate clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver samples input data using the rising and falling edge of the baud rate clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCFG</name>
|
|
<description>Match Configuration</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Address Match Wakeup</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Idle Match Wakeup</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Match On and Match Off</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIDMAE</name>
|
|
<description>Receiver Idle DMA Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDMAE</name>
|
|
<description>Receiver Full DMA Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDMAE</name>
|
|
<description>Transmitter DMA Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA request disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA request enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OSR</name>
|
|
<description>Oversampling Ratio</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M10</name>
|
|
<description>10-bit Mode select</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 7-bit to 9-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 10-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN2</name>
|
|
<description>Match Address Mode Enable 2</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables automatic address matching or data matching mode for MATCH[MA2].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MAEN1</name>
|
|
<description>Match Address Mode Enable 1</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables automatic address matching or data matching mode for MATCH[MA1].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<description>LPUART Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA2F</name>
|
|
<description>Match 2 Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is not equal to MA2</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is equal to MA2</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA1F</name>
|
|
<description>Match 1 Flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Received data is not equal to MA1</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Received data is equal to MA1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PF</name>
|
|
<description>Parity Error Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing Error Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No framing error detected. This does not guarantee the framing is correct.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Framing error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>Noise Flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No noise detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Noise detected in the received character in LPUART_DATA.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OR</name>
|
|
<description>Receiver Overrun Flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No overrun.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive overrun (new LPUART data lost).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>Idle Line Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No idle line detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle line was detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RDRF</name>
|
|
<description>Receive Data Register Full Flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data buffer empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data buffer full.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission Complete Flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter active (sending data, a preamble, or a break).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter idle (transmission activity complete).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TDRE</name>
|
|
<description>Transmit Data Register Empty Flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data buffer full.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data buffer empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RAF</name>
|
|
<description>Receiver Active Flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPUART receiver idle waiting for a start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART receiver active (RXD input not idle).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDE</name>
|
|
<description>LIN Break Detection Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LIN break detect is disabled, normal break character can be detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BRK13</name>
|
|
<description>Break Character Generation Length</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Break character is transmitted with length of 9 to 13 bit times.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Break character is transmitted with length of 12 to 15 bit times.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWUID</name>
|
|
<description>Receive Wake Up Idle Detect</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>Receive Data Inversion</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>MSB First</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEDGIF</name>
|
|
<description>RXD Pin Active Edge Interrupt Flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No active edge on the receive pin has occurred.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>An active edge on the receive pin has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LBKDIF</name>
|
|
<description>LIN Break Detect Interrupt Flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No LIN break character has been detected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LIN break character has been detected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>LPUART Control Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PT</name>
|
|
<description>Parity Type</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Even parity.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Odd parity.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No hardware parity generation or checking.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Parity enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILT</name>
|
|
<description>Idle Line Type Select</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Idle character bit count starts after start bit.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Idle character bit count starts after stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver Wakeup Method Select</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Configures RWU for idle-line wakeup.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Configures RWU with address-mark wakeup.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>9-Bit or 8-Bit Mode Select</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 8-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 9-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSRC</name>
|
|
<description>Receiver Source Select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DOZEEN</name>
|
|
<description>Doze Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>LPUART is enabled in Doze mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART is disabled in Doze mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOOPS</name>
|
|
<description>Loop Mode Select</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal operation - RXD and TXD use separate pins.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IDLECFG</name>
|
|
<description>Idle Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>1 idle character</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>2 idle characters</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>4 idle characters</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>8 idle characters</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>16 idle characters</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>32 idle characters</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>64 idle characters</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>128 idle characters</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>M7</name>
|
|
<description>7-Bit Mode Select</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver and transmitter use 8-bit to 10-bit data characters.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver and transmitter use 7-bit data characters.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA2IE</name>
|
|
<description>Match 2 Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MA2F interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MA2F interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MA1IE</name>
|
|
<description>Match 1 Interrupt Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MA1F interrupt disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MA1F interrupt enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>Send Break</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal transmitter operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Queue break character(s) to be sent.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver Wakeup Control</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Normal receiver operation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPUART receiver in standby waiting for wakeup condition.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver Enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ILIE</name>
|
|
<description>Idle Line Interrupt Enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from IDLE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when IDLE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>Receiver Interrupt Enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from RDRF disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when RDRF flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission Complete Interrupt Enable for</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TC disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TC flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Transmit Interrupt Enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupts from TDRE disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when TDRE flag is 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>Parity Error Interrupt Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>PF interrupts disabled; use polling).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when PF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>Framing Error Interrupt Enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>FE interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when FE is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NEIE</name>
|
|
<description>Noise Error Interrupt Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>NF interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when NF is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ORIE</name>
|
|
<description>Overrun Interrupt Enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>OR interrupts disabled; use polling.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Hardware interrupt requested when OR is set.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>Transmit Data Inversion</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit data not inverted.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit data inverted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXDIR</name>
|
|
<description>TXD Pin Direction in Single-Wire Mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXD pin is an input in single-wire mode.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXD pin is an output in single-wire mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>R9T8</name>
|
|
<description>Receive Bit 9 / Transmit Bit 8</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T9</name>
|
|
<description>Receive Bit 8 / Transmit Bit 9</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<description>LPUART Data Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>R0T0</name>
|
|
<description>R0T0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R1T1</name>
|
|
<description>R1T1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R2T2</name>
|
|
<description>R2T2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R3T3</name>
|
|
<description>R3T3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R4T4</name>
|
|
<description>R4T4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R5T5</name>
|
|
<description>R5T5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R6T6</name>
|
|
<description>R6T6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R7T7</name>
|
|
<description>R7T7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R8T8</name>
|
|
<description>R8T8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>R9T9</name>
|
|
<description>R9T9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDLINE</name>
|
|
<description>Idle Line</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receiver was not idle before receiving this character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receiver was idle before receiving this character.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer Empty</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer contains valid data.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty, data returned on read is not valid.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FRETSC</name>
|
|
<description>Frame Error / Transmit Special Character</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a frame error on read, transmit a normal character on write.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a frame error, transmit an idle or break character on transmit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PARITYE</name>
|
|
<description>PARITYE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without a parity error.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The dataword was received with a parity error.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NOISY</name>
|
|
<description>NOISY</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The dataword was received without noise.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The data was received with noise.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATCH</name>
|
|
<description>LPUART Match Address Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MA1</name>
|
|
<description>Match Address 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MA2</name>
|
|
<description>Match Address 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODIR</name>
|
|
<description>LPUART Modem IrDA Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXCTSE</name>
|
|
<description>Transmitter clear-to-send enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS has no effect on the transmitter.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSE</name>
|
|
<description>Transmitter request-to-send enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The transmitter has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXRTSPOL</name>
|
|
<description>Transmitter request-to-send polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmitter RTS is active low.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmitter RTS is active high.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXRTSE</name>
|
|
<description>Receiver request-to-send enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The receiver has no effect on RTS.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSC</name>
|
|
<description>Transmit CTS Configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS input is sampled at the start of each character.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CTS input is sampled when the transmitter is idle.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXCTSSRC</name>
|
|
<description>Transmit CTS Source</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>CTS input is the CTS_B pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>CTS input is the inverted Receiver Match result.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RTSWATER</name>
|
|
<description>Receive RTS Configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TNP</name>
|
|
<description>Transmitter narrow pulse</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>1/OSR.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>2/OSR.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>3/OSR.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>4/OSR.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Infrared enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>IR disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>IR enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO</name>
|
|
<description>LPUART FIFO Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC00011</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RXFIFOSIZE</name>
|
|
<description>Receive FIFO. Buffer Depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Receive FIFO/Buffer depth = 1 dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Receive FIFO/Buffer depth = 4 datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Receive FIFO/Buffer depth = 8 datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Receive FIFO/Buffer depth = 16 datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Receive FIFO/Buffer depth = 32 datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Receive FIFO/Buffer depth = 64 datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Receive FIFO/Buffer depth = 128 datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Receive FIFO/Buffer depth = 256 datawords.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFE</name>
|
|
<description>Receive FIFO Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFIFOSIZE</name>
|
|
<description>Transmit FIFO. Buffer Depth</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Transmit FIFO/Buffer depth = 1 dataword.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Transmit FIFO/Buffer depth = 4 datawords.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Transmit FIFO/Buffer depth = 8 datawords.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Transmit FIFO/Buffer depth = 16 datawords.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Transmit FIFO/Buffer depth = 32 datawords.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Transmit FIFO/Buffer depth = 64 datawords.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Transmit FIFO/Buffer depth = 128 datawords.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Transmit FIFO/Buffer depth = 256 datawords</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXUFE</name>
|
|
<description>Receive FIFO Underflow Interrupt Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>RXUF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>RXUF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOFE</name>
|
|
<description>Transmit FIFO Overflow Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>TXOF flag does not generate an interrupt to the host.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>TXOF flag generates an interrupt to the host.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXIDEN</name>
|
|
<description>Receiver Idle Empty Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Disable RDRF assertion due to partially filled FIFO when receiver is idle.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXFLUSH</name>
|
|
<description>Receive FIFO/Buffer Flush</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the receive FIFO/buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXFLUSH</name>
|
|
<description>Transmit FIFO/Buffer Flush</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No flush operation occurs.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All data in the transmit FIFO/Buffer is cleared out.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXUF</name>
|
|
<description>Receiver Buffer Underflow Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one receive buffer underflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXOF</name>
|
|
<description>Transmitter Buffer Overflow Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>At least one transmit buffer overflow has occurred since the last time the flag was cleared.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RXEMPT</name>
|
|
<description>Receive Buffer/FIFO Empty</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Receive buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Receive buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TXEMPT</name>
|
|
<description>Transmit Buffer/FIFO Empty</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Transmit buffer is not empty.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Transmit buffer is empty.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WATER</name>
|
|
<description>LPUART Watermark Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TXWATER</name>
|
|
<description>Transmit Watermark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXCOUNT</name>
|
|
<description>Transmit Counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXWATER</name>
|
|
<description>Receive Watermark</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXCOUNT</name>
|
|
<description>Receive Counter</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMP0</name>
|
|
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
|
|
<groupName>CMP</groupName>
|
|
<prependToName>CMP0_</prependToName>
|
|
<baseAddress>0x40073000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP0</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>CMP Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HYSTCTR</name>
|
|
<description>Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The hard block output has level 0 hysteresis internally.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The hard block output has level 1 hysteresis internally.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The hard block output has level 2 hysteresis internally.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The hard block output has level 3 hysteresis internally.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET</name>
|
|
<description>Comparator hard block offset control. See chip data sheet to get the actual offset value with each level</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The comparator hard block output has level 0 offset internally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The comparator hard block output has level 1 offset internally.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTER_CNT</name>
|
|
<description>Filter Sample Count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 consecutive sample must agree (comparator output is simply sampled).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 consecutive samples must agree.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 consecutive samples must agree.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 consecutive samples must agree.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>5 consecutive samples must agree.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>6 consecutive samples must agree.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>7 consecutive samples must agree.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator Module Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Analog Comparator is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Analog Comparator is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPE</name>
|
|
<description>Comparator Output Pin Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COS</name>
|
|
<description>Comparator Output Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set CMPO to equal COUT (filtered comparator output).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set CMPO to equal COUTA (unfiltered comparator output).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVT</name>
|
|
<description>Comparator invert</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not invert the comparator output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverts the comparator output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Power Mode Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low Speed (LS) comparison mode is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>Windowing Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Windowing mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Windowing mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Sample Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sampling mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sampling mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FPR</name>
|
|
<description>Filter Sample Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COUT</name>
|
|
<description>Analog Comparator Output</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFF</name>
|
|
<description>Analog Comparator Flag Falling</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A falling edge has not been detected on COUT.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A falling edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFR</name>
|
|
<description>Analog Comparator Flag Rising</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A rising edge has not been detected on COUT.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A rising edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEF</name>
|
|
<description>Comparator Interrupt Enable Falling</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IER</name>
|
|
<description>Comparator Interrupt Enable Rising</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>CMP Control Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VOSEL</name>
|
|
<description>DAC Output Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Minus Input MUX Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Plus Input MUX Control</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VRSEL</name>
|
|
<description>Supply Voltage Reference Source Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Vin1 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vin2 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHN0</name>
|
|
<description>Channel 0 input enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN1</name>
|
|
<description>Channel 1 input enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN2</name>
|
|
<description>Channel 2 input enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN3</name>
|
|
<description>Channel 3 input enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN4</name>
|
|
<description>Channel 4 input enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN5</name>
|
|
<description>Channel 5 input enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN6</name>
|
|
<description>Channel 6 input enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN7</name>
|
|
<description>Channel 7 input enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INNSEL</name>
|
|
<description>Selection of the input to the negative port of the comparator</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>IN0, from the 8-bit DAC output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>IN1, from the analog 8-1 mux</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>Selection of the input to the positive port of the comparator</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>IN0, from the 8-bit DAC output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>IN1, from the analog 8-1 mux</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACOE</name>
|
|
<description>DAC output Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC output is disabled to go outside.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC output is enabled to go outside.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>CMP Control Register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACOn</name>
|
|
<description>The result of the input comparison for channel n</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INITMOD</name>
|
|
<description>Comparator and DAC initialization delay modulus.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000000</name>
|
|
<description>The modulus is set to 64(same with 111111).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSAM</name>
|
|
<description>Number of sample clocks</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 input changed flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 input changed flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 input changed flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 input changed flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 input changed flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 input changed flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 input changed flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 input changed flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FXMXCH</name>
|
|
<description>Fixed channel selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Channel 0 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Channel 1 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Channel 2 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Channel 3 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Channel 4 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Channel 5 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Channel 6 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Channel 7 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FXMP</name>
|
|
<description>Fixed MUX Port</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The Plus port is fixed. Only the inputs to the Minus port are swept in each round.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The Minus port is fixed. Only the inputs to the Plus port are swept in each round.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRIE</name>
|
|
<description>Round-Robin interrupt enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The round-robin interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The round-robin interrupt is enabled when a comparison result changes from the last sample.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRE</name>
|
|
<description>Round-Robin Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Round-robin operation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Round-robin operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CMP1</name>
|
|
<description>High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)</description>
|
|
<groupName>CMP</groupName>
|
|
<prependToName>CMP1_</prependToName>
|
|
<baseAddress>0x40074000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0xC</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CMP1</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C0</name>
|
|
<description>CMP Control Register 0</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>HYSTCTR</name>
|
|
<description>Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The hard block output has level 0 hysteresis internally.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The hard block output has level 1 hysteresis internally.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The hard block output has level 2 hysteresis internally.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The hard block output has level 3 hysteresis internally.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET</name>
|
|
<description>Comparator hard block offset control. See chip data sheet to get the actual offset value with each level</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The comparator hard block output has level 0 offset internally.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The comparator hard block output has level 1 offset internally.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FILTER_CNT</name>
|
|
<description>Filter Sample Count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>1 consecutive sample must agree (comparator output is simply sampled).</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>2 consecutive samples must agree.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>3 consecutive samples must agree.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>4 consecutive samples must agree.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>5 consecutive samples must agree.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>6 consecutive samples must agree.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>7 consecutive samples must agree.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Comparator Module Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Analog Comparator is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Analog Comparator is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>OPE</name>
|
|
<description>Comparator Output Pin Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COS</name>
|
|
<description>Comparator Output Select</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Set CMPO to equal COUT (filtered comparator output).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Set CMPO to equal COUTA (unfiltered comparator output).</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INVT</name>
|
|
<description>Comparator invert</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Does not invert the comparator output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Inverts the comparator output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PMODE</name>
|
|
<description>Power Mode Select</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low Speed (LS) comparison mode is selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WE</name>
|
|
<description>Windowing Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Windowing mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Windowing mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Sample Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Sampling mode is not selected.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Sampling mode is selected.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FPR</name>
|
|
<description>Filter Sample Period</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COUT</name>
|
|
<description>Analog Comparator Output</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CFF</name>
|
|
<description>Analog Comparator Flag Falling</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A falling edge has not been detected on COUT.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A falling edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFR</name>
|
|
<description>Analog Comparator Flag Rising</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A rising edge has not been detected on COUT.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A rising edge on COUT has occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IEF</name>
|
|
<description>Comparator Interrupt Enable Falling</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>IER</name>
|
|
<description>Comparator Interrupt Enable Rising</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA Enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DMA is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DMA is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1</name>
|
|
<description>CMP Control Register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>VOSEL</name>
|
|
<description>DAC Output Voltage Select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSEL</name>
|
|
<description>Minus Input MUX Control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PSEL</name>
|
|
<description>Plus Input MUX Control</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>IN0</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>IN1</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>IN2</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>IN3</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>IN4</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>IN5</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>IN6</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>IN7</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>VRSEL</name>
|
|
<description>Supply Voltage Reference Source Select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Vin1 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Vin2 is selected as resistor ladder network supply reference Vin.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC Enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CHN0</name>
|
|
<description>Channel 0 input enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN1</name>
|
|
<description>Channel 1 input enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN2</name>
|
|
<description>Channel 2 input enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN3</name>
|
|
<description>Channel 3 input enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN4</name>
|
|
<description>Channel 4 input enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN5</name>
|
|
<description>Channel 5 input enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN6</name>
|
|
<description>Channel 6 input enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CHN7</name>
|
|
<description>Channel 7 input enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INNSEL</name>
|
|
<description>Selection of the input to the negative port of the comparator</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>IN0, from the 8-bit DAC output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>IN1, from the analog 8-1 mux</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>Selection of the input to the positive port of the comparator</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>IN0, from the 8-bit DAC output</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>IN1, from the analog 8-1 mux</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DACOE</name>
|
|
<description>DAC output Enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>DAC output is disabled to go outside.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>DAC output is enabled to go outside.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2</name>
|
|
<description>CMP Control Register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACOn</name>
|
|
<description>The result of the input comparison for channel n</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INITMOD</name>
|
|
<description>Comparator and DAC initialization delay modulus.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000000</name>
|
|
<description>The modulus is set to 64(same with 111111).</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NSAM</name>
|
|
<description>Number of sample clocks</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CH0F</name>
|
|
<description>Channel 0 input changed flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH1F</name>
|
|
<description>Channel 1 input changed flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH2F</name>
|
|
<description>Channel 2 input changed flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH3F</name>
|
|
<description>Channel 3 input changed flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH4F</name>
|
|
<description>Channel 4 input changed flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH5F</name>
|
|
<description>Channel 5 input changed flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH6F</name>
|
|
<description>Channel 6 input changed flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CH7F</name>
|
|
<description>Channel 7 input changed flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FXMXCH</name>
|
|
<description>Fixed channel selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Channel 0 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>001</name>
|
|
<description>Channel 1 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#001</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Channel 2 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Channel 3 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Channel 4 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Channel 5 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Channel 6 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>111</name>
|
|
<description>Channel 7 is selected as the fixed reference input for the fixed mux port.</description>
|
|
<value>#111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>FXMP</name>
|
|
<description>Fixed MUX Port</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The Plus port is fixed. Only the inputs to the Minus port are swept in each round.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The Minus port is fixed. Only the inputs to the Plus port are swept in each round.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRIE</name>
|
|
<description>Round-Robin interrupt enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The round-robin interrupt is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The round-robin interrupt is enabled when a comparison result changes from the last sample.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RRE</name>
|
|
<description>Round-Robin Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Round-robin operation is disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Round-robin operation is enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMC</name>
|
|
<description>PMC</description>
|
|
<prependToName>PMC_</prependToName>
|
|
<baseAddress>0x4007D000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LVD_LVW</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>LVDSC1</name>
|
|
<description>Low Voltage Detect Status and Control 1 Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVDRE</name>
|
|
<description>Low Voltage Detect Reset Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No system resets on low voltage detect events.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If the supply voltage falls below VLVD, a system reset will be generated.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDIE</name>
|
|
<description>Low Voltage Detect Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupt disabled (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when LVDF = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVDACK</name>
|
|
<description>Low Voltage Detect Acknowledge</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDF</name>
|
|
<description>Low Voltage Detect Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-voltage event not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-voltage event detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LVDSC2</name>
|
|
<description>Low Voltage Detect Status and Control 2 Register</description>
|
|
<addressOffset>0x1</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVWIE</name>
|
|
<description>Low-Voltage Warning Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Hardware interrupt disabled (use polling)</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request a hardware interrupt when LVWF=1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LVWACK</name>
|
|
<description>Low-Voltage Warning Acknowledge</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LVWF</name>
|
|
<description>Low-Voltage Warning Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low-voltage warning event not detected</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low-voltage warning event detected</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REGSC</name>
|
|
<description>Regulator Status and Control Register</description>
|
|
<addressOffset>0x2</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BIASEN</name>
|
|
<description>Bias Enable Bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Biasing disabled, core logic can run in full performance</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Biasing enabled, core logic is slower and there are restrictions in allowed system clock speed (see device level specification for details)</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REGFPM</name>
|
|
<description>Regulator in Full Performance Mode Status Bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Regulator is in low power mode or transition to/from</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Regulator is in full performance mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPOSTAT</name>
|
|
<description>LPO Status Bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low power oscillator in low phase</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low power oscillator in high phase</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LPODIS</name>
|
|
<description>LPO Disable Bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Low power oscillator enabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Low power oscillator disabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPOTRIM</name>
|
|
<description>Low Power Oscillator Trim Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>8</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LPOTRIM</name>
|
|
<description>LPO trimming bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SMC</name>
|
|
<description>System Mode Controller</description>
|
|
<prependToName>SMC_</prependToName>
|
|
<baseAddress>0x4007E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>SMC Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Specification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Standard features implemented</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>SMC Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EHSRUN</name>
|
|
<description>HSRUN feature exists</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELLS</name>
|
|
<description>LLS feature exists</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELLS2</name>
|
|
<description>LLS2 feature exists</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EVLLS0</name>
|
|
<description>VLLS0 feature exists</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMPROT</name>
|
|
<description>Power Mode Protection register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AVLP</name>
|
|
<description>Allow Very-Low-Power Modes</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>VLPR, VLPW, and VLPS are not allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>VLPR, VLPW, and VLPS are allowed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMCTRL</name>
|
|
<description>Power Mode Control register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>STOPM</name>
|
|
<description>Stop Mode Control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>000</name>
|
|
<description>Normal Stop (STOP)</description>
|
|
<value>#000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Very-Low-Power Stop (VLPS)</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>110</name>
|
|
<description>Reseved</description>
|
|
<value>#110</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>STOPA</name>
|
|
<description>Stop Aborted</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The previous stop mode entry was successful.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The previous stop mode entry was aborted.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RUNM</name>
|
|
<description>Run Mode Control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Normal Run mode (RUN)</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Very-Low-Power Run mode (VLPR)</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STOPCTRL</name>
|
|
<description>Stop Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x3</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSTOPO</name>
|
|
<description>Partial Stop Option</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>STOP - Normal Stop mode</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>PSTOP1 - Partial Stop with both system and bus clocks disabled</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>PSTOP2 - Partial Stop with system clock disabled and bus clock enabled</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMSTAT</name>
|
|
<description>Power Mode Status register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PMSTAT</name>
|
|
<description>Power Mode Status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RCM</name>
|
|
<description>Reset Control Module</description>
|
|
<prependToName>RCM_</prependToName>
|
|
<baseAddress>0x4007F000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RCM</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>VERID</name>
|
|
<description>Version ID Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x3000003</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FEATURE</name>
|
|
<description>Feature Specification Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Standard feature set.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MINOR</name>
|
|
<description>Minor Version Number</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MAJOR</name>
|
|
<description>Major Version Number</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<description>Parameter Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2EEE</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>EWAKEUP</name>
|
|
<description>Existence of SRS[WAKEUP] status indication feature</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELVD</name>
|
|
<description>Existence of SRS[LVD] status indication feature</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELOC</name>
|
|
<description>Existence of SRS[LOC] status indication feature</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELOL</name>
|
|
<description>Existence of SRS[LOL] status indication feature</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EWDOG</name>
|
|
<description>Existence of SRS[WDOG] status indication feature</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPIN</name>
|
|
<description>Existence of SRS[PIN] status indication feature</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EPOR</name>
|
|
<description>Existence of SRS[POR] status indication feature</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EJTAG</name>
|
|
<description>Existence of SRS[JTAG] status indication feature</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ELOCKUP</name>
|
|
<description>Existence of SRS[LOCKUP] status indication feature</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESW</name>
|
|
<description>Existence of SRS[SW] status indication feature</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EMDM_AP</name>
|
|
<description>Existence of SRS[MDM_AP] status indication feature</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESACKERR</name>
|
|
<description>Existence of SRS[SACKERR] status indication feature</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ETAMPER</name>
|
|
<description>Existence of SRS[TAMPER] status indication feature</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ECORE1</name>
|
|
<description>Existence of SRS[CORE1] status indication feature</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The feature is not available.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The feature is available.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRS</name>
|
|
<description>System Reset Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x82</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LVD</name>
|
|
<description>Low-Voltage Detect Reset or High-Voltage Detect Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by LVD trip, HVD trip or POR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by LVD trip, HVD trip or POR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOC</name>
|
|
<description>Loss-of-Clock Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by a loss of external clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by a loss of external clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOL</name>
|
|
<description>Loss-of-Lock Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by a loss of lock in the PLL</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by a loss of lock in the PLL</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDOG</name>
|
|
<description>Watchdog</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by watchdog timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by watchdog timeout</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>External Reset Pin</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by external reset pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by external reset pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>POR</name>
|
|
<description>Power-On Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by POR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by POR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCKUP</name>
|
|
<description>Core Lockup</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by core LOCKUP event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by core LOCKUP event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>Software</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDM_AP</name>
|
|
<description>MDM-AP System Reset Request</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset was not caused by host debugger system setting of the System Reset Request bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset was caused by host debugger system setting of the System Reset Request bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SACKERR</name>
|
|
<description>Stop Acknowledge Error</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RPC</name>
|
|
<description>Reset Pin Control register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RSTFLTSRW</name>
|
|
<description>Reset Pin Filter Select in Run and Wait Modes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>All filtering disabled</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Bus clock filter enabled for normal operation</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>LPO clock filter enabled for normal operation</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTFLTSS</name>
|
|
<description>Reset Pin Filter Select in Stop Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All filtering disabled</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>LPO clock filter enabled</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RSTFLTSEL</name>
|
|
<description>Reset Pin Filter Bus Clock Select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MR</name>
|
|
<description>Mode Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BOOTROM</name>
|
|
<description>Boot ROM Configuration</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Boot from Flash</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Boot from ROM due to BOOTCFG0 pin assertion / Reserved if no Boot pin</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Boot form ROM due to FOPT[7] configuration</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Boot from ROM due to both BOOTCFG0 pin assertion and FOPT[7] configuration</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FM</name>
|
|
<description>Force Mode Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FORCEROM</name>
|
|
<description>Force ROM Boot</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>No effect</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Force boot from ROM with RCM_MR[1] set.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Force boot from ROM with RCM_MR[2] set.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Force boot from ROM with RCM_MR[2:1] set.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSRS</name>
|
|
<description>Sticky System Reset Status Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x82</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SLVD</name>
|
|
<description>Sticky Low-Voltage Detect Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by LVD trip or POR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by LVD trip or POR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOC</name>
|
|
<description>Sticky Loss-of-Clock Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by a loss of external clock.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by a loss of external clock.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOL</name>
|
|
<description>Sticky Loss-of-Lock Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by a loss of lock in the PLL</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by a loss of lock in the PLL</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SWDOG</name>
|
|
<description>Sticky Watchdog</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by watchdog timeout</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by watchdog timeout</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPIN</name>
|
|
<description>Sticky External Reset Pin</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by external reset pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by external reset pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SPOR</name>
|
|
<description>Sticky Power-On Reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by POR</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by POR</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SLOCKUP</name>
|
|
<description>Sticky Core Lockup</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by core LOCKUP event</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by core LOCKUP event</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSW</name>
|
|
<description>Sticky Software</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by software setting of SYSRESETREQ bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SMDM_AP</name>
|
|
<description>Sticky MDM-AP System Reset Request</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset was not caused by host debugger system setting of the System Reset Request bit</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset was caused by host debugger system setting of the System Reset Request bit</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SSACKERR</name>
|
|
<description>Sticky Stop Acknowledge Error</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by peripheral failure to acknowledge attempt to enter stop mode</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by peripheral failure to acknowledge attempt to enter stop mode</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRIE</name>
|
|
<description>System Reset Interrupt Enable Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DELAY</name>
|
|
<description>Reset Delay Time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>10 LPO cycles</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>34 LPO cycles</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>130 LPO cycles</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>514 LPO cycles</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOC</name>
|
|
<description>Loss-of-Clock Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOL</name>
|
|
<description>Loss-of-Lock Interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>WDOG</name>
|
|
<description>Watchdog Interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PIN</name>
|
|
<description>External Reset Pin Interrupt</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reset not caused by external reset pin</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Reset caused by external reset pin</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>GIE</name>
|
|
<description>Global Interrupt Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>All interrupt sources disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>All interrupt sources enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>LOCKUP</name>
|
|
<description>Core Lockup Interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>Software Interrupt</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MDM_AP</name>
|
|
<description>MDM-AP System Reset Request</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SACKERR</name>
|
|
<description>Stop Acknowledge Error Interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Interrupt disabled.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Interrupt enabled.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOA_</prependToName>
|
|
<baseAddress>0x400FF000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTAE</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOB</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOB_</prependToName>
|
|
<baseAddress>0x400FF040</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTBCD</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOC</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOC_</prependToName>
|
|
<baseAddress>0x400FF080</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTBCD</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOD</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOD_</prependToName>
|
|
<baseAddress>0x400FF0C0</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTBCD</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOE</name>
|
|
<description>General Purpose Input/Output</description>
|
|
<groupName>GPIO</groupName>
|
|
<prependToName>GPIOE_</prependToName>
|
|
<baseAddress>0x400FF100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x18</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PORTAE</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PDOR</name>
|
|
<description>Port Data Output Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDO</name>
|
|
<description>Port Data Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Logic level 0 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Logic level 1 is driven on pin, provided pin is configured for general-purpose output.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSOR</name>
|
|
<description>Port Set Output Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTSO</name>
|
|
<description>Port Set Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCOR</name>
|
|
<description>Port Clear Output Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTCO</name>
|
|
<description>Port Clear Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is cleared to logic 0.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTOR</name>
|
|
<description>Port Toggle Output Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PTTO</name>
|
|
<description>Port Toggle Output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Corresponding bit in PDORn does not change.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Corresponding bit in PDORn is set to the inverse of its existing logic state.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDIR</name>
|
|
<description>Port Data Input Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDI</name>
|
|
<description>Port Data Input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin logic level is logic 0, or is not configured for use by digital function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin logic level is logic 1.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDDR</name>
|
|
<description>Port Data Direction Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PDD</name>
|
|
<description>Port Data Direction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Pin is configured as general-purpose input, for the GPIO function.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Pin is configured as general-purpose output, for the GPIO function.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MTB</name>
|
|
<description>Micro Trace Buffer</description>
|
|
<prependToName>MTB_</prependToName>
|
|
<baseAddress>0xF0000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>POSITION</name>
|
|
<description>MTB Position Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x3</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>WRAP</name>
|
|
<description>WRAP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POINTER</name>
|
|
<description>Trace Packet Address Pointer[28:0]</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MASTER</name>
|
|
<description>MTB Master Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80</resetValue>
|
|
<resetMask>0xFFFFFFE0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSTARTEN</name>
|
|
<description>Trace Start Input Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSTOPEN</name>
|
|
<description>Trace Stop Input Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SFRWPRIV</name>
|
|
<description>Special Function Register Write Privilege</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RAMPRIV</name>
|
|
<description>RAM Privilege</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HALTREQ</name>
|
|
<description>Halt Request</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Main Trace Enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLOW</name>
|
|
<description>MTB Flow Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x4</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AUTOSTOP</name>
|
|
<description>AUTOSTOP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOHALT</name>
|
|
<description>AUTOHALT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WATERMARK</name>
|
|
<description>WATERMARK[28:0]</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BASE</name>
|
|
<description>MTB Base Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BASEADDR</name>
|
|
<description>BASEADDR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MODECTRL</name>
|
|
<description>Integration Mode Control Register</description>
|
|
<addressOffset>0xF00</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MODECTRL</name>
|
|
<description>MODECTRL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAGSET</name>
|
|
<description>Claim TAG Set Register</description>
|
|
<addressOffset>0xFA0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAGSET</name>
|
|
<description>TAGSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAGCLEAR</name>
|
|
<description>Claim TAG Clear Register</description>
|
|
<addressOffset>0xFA4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>TAGCLEAR</name>
|
|
<description>TAGCLEAR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCKACCESS</name>
|
|
<description>Lock Access Register</description>
|
|
<addressOffset>0xFB0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKACCESS</name>
|
|
<description>Hardwired to 0x0000_0000</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCKSTAT</name>
|
|
<description>Lock Status Register</description>
|
|
<addressOffset>0xFB4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKSTAT</name>
|
|
<description>LOCKSTAT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AUTHSTAT</name>
|
|
<description>Authentication Status Register</description>
|
|
<addressOffset>0xFB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>BIT0</name>
|
|
<description>Connected to DBGEN.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BIT2</name>
|
|
<description>BIT2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICEARCH</name>
|
|
<description>Device Architecture Register</description>
|
|
<addressOffset>0xFBC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x47700A31</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICEARCH</name>
|
|
<description>DEVICEARCH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICECFG</name>
|
|
<description>Device Configuration Register</description>
|
|
<addressOffset>0xFC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICECFG</name>
|
|
<description>DEVICECFG</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICETYPID</name>
|
|
<description>Device Type Identifier Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x31</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICETYPID</name>
|
|
<description>DEVICETYPID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
|
|
<name>PERIPHID%s</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>PERIPHID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>COMPID%s</name>
|
|
<description>Component ID Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPID</name>
|
|
<description>Component ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MTBDWT</name>
|
|
<description>MTB data watchpoint and trace</description>
|
|
<prependToName>MTBDWT_</prependToName>
|
|
<baseAddress>0xF0001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<description>MTB DWT Control Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2F000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DWTCFGCTRL</name>
|
|
<description>DWT configuration controls</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>28</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NUMCMP</name>
|
|
<description>Number of comparators</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>COMP%s</name>
|
|
<description>MTB_DWT Comparator Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Reference value for comparison</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>2</dim>
|
|
<dimIncrement>0x10</dimIncrement>
|
|
<dimIndex>0,1</dimIndex>
|
|
<name>MASK%s</name>
|
|
<description>MTB_DWT Comparator Mask Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>MASK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCT0</name>
|
|
<description>MTB_DWT Comparator Function Register 0</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<description>Function</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Instruction fetch.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Data operand read.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Data operand write.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Data operand (read + write).</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVMATCH</name>
|
|
<description>Data Value Match</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Perform address comparison.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Perform data value comparison.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVSIZE</name>
|
|
<description>Data Value Size</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00</name>
|
|
<description>Byte.</description>
|
|
<value>#00</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>01</name>
|
|
<description>Halfword.</description>
|
|
<value>#01</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>10</name>
|
|
<description>Word.</description>
|
|
<value>#10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11</name>
|
|
<description>Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.</description>
|
|
<value>#11</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DATAVADDR0</name>
|
|
<description>Data Value Address 0</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>Comparator match</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No match.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Match occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCT1</name>
|
|
<description>MTB_DWT Comparator Function Register 1</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>FUNCTION</name>
|
|
<description>Function</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0000</name>
|
|
<description>Disabled.</description>
|
|
<value>#0000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0100</name>
|
|
<description>Instruction fetch.</description>
|
|
<value>#0100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0101</name>
|
|
<description>Data operand read.</description>
|
|
<value>#0101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0110</name>
|
|
<description>Data operand write.</description>
|
|
<value>#0110</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>0111</name>
|
|
<description>Data operand (read + write).</description>
|
|
<value>#0111</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>MATCHED</name>
|
|
<description>Comparator match</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No match.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Match occurred.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBCTRL</name>
|
|
<description>MTB_DWT Trace Buffer Control Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ACOMP0</name>
|
|
<description>Action based on Comparator 0 match</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ACOMP1</name>
|
|
<description>Action based on Comparator 1 match</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NUMCOMP</name>
|
|
<description>Number of Comparators</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICECFG</name>
|
|
<description>Device Configuration Register</description>
|
|
<addressOffset>0xFC8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICECFG</name>
|
|
<description>DEVICECFG</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEVICETYPID</name>
|
|
<description>Device Type Identifier Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x4</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DEVICETYPID</name>
|
|
<description>DEVICETYPID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
|
|
<name>PERIPHID%s</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>PERIPHID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>COMPID%s</name>
|
|
<description>Component ID Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPID</name>
|
|
<description>Component ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ROM</name>
|
|
<description>System ROM</description>
|
|
<prependToName>ROM_</prependToName>
|
|
<baseAddress>0xF0002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<dim>3</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2</dimIndex>
|
|
<name>ENTRY%s</name>
|
|
<description>Entry</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ENTRY</name>
|
|
<description>ENTRY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TABLEMARK</name>
|
|
<description>End of Table Marker Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>MARK</name>
|
|
<description>MARK</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYSACCESS</name>
|
|
<description>System Access Register</description>
|
|
<addressOffset>0xFCC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x1</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SYSACCESS</name>
|
|
<description>SYSACCESS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>8</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>4,5,6,7,0,1,2,3</dimIndex>
|
|
<name>PERIPHID%s</name>
|
|
<description>Peripheral ID Register</description>
|
|
<addressOffset>0xFD0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PERIPHID</name>
|
|
<description>PERIPHID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<dim>4</dim>
|
|
<dimIncrement>0x4</dimIncrement>
|
|
<dimIndex>0,1,2,3</dimIndex>
|
|
<name>COMPID%s</name>
|
|
<description>Component ID Register</description>
|
|
<addressOffset>0xFF0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>COMPID</name>
|
|
<description>Component ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MCM</name>
|
|
<description>Core Platform Miscellaneous Control Module</description>
|
|
<prependToName>MCM_</prependToName>
|
|
<baseAddress>0xF0003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x8</offset>
|
|
<size>0x7C</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PLASC</name>
|
|
<description>Crossbar Switch (AXBS) Slave Configuration</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x7</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ASC</name>
|
|
<description>Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A bus slave connection to AXBS input port n is absent.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus slave connection to AXBS input port n is present.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLAMC</name>
|
|
<description>Crossbar Switch (AXBS) Master Configuration</description>
|
|
<addressOffset>0xA</addressOffset>
|
|
<size>16</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x5</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>AMC</name>
|
|
<description>Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A bus master connection to AXBS input port n is absent</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A bus master connection to AXBS input port n is present</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLACR</name>
|
|
<description>Platform Control Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x250</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARB</name>
|
|
<description>Arbitration select</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Fixed-priority arbitration for the crossbar masters</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Round-robin arbitration for the crossbar masters</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CFCC</name>
|
|
<description>Clear Flash Controller Cache</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DFCDA</name>
|
|
<description>Disable Flash Controller Data Caching</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller data caching</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller data caching.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCIC</name>
|
|
<description>Disable Flash Controller Instruction Caching</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller instruction caching.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller instruction caching.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCC</name>
|
|
<description>Disable Flash Controller Cache</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller cache.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller cache.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>EFDS</name>
|
|
<description>Enable Flash Data Speculation</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable flash data speculation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable flash data speculation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFCS</name>
|
|
<description>Disable Flash Controller Speculation</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Enable flash controller speculation.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Disable flash controller speculation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ESFC</name>
|
|
<description>Enable Stalling Flash Controller</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Disable stalling flash controller when flash is busy.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Enable stalling flash controller when flash is busy.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID</name>
|
|
<description>Process ID register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>M0_PID For MPU</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reserved for privileged secure tasks</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPO</name>
|
|
<description>Compute Operation Control Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CPOREQ</name>
|
|
<description>Compute Operation Request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Request is cleared.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Request Compute Operation.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOACK</name>
|
|
<description>Compute Operation Acknowledge</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Compute operation entry has not completed or compute operation exit has completed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Compute operation entry has completed or compute operation exit has not completed.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>CPOWOI</name>
|
|
<description>Compute Operation Wake-up on Interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No effect.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>When set, the CPOREQ is cleared on any interrupt or exception vector fetch.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MATCR</name>
|
|
<description>Master Attribute Configuration Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0xFFFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ATC0</name>
|
|
<description>Attribute Configuration Master n</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00x</name>
|
|
<description>Master attributes are statically forced to {privileged, secure}.</description>
|
|
<value>#00x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Master attributes are statically forced to {user, secure}.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Master attributes are statically forced to {user, nonsecure}.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Enable master attribute {privileged or user} and statically force {secure}.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Enable master attribute {privileged or user} and statically force {nonsecure}.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11x</name>
|
|
<description>Enable master attribute {privileged or user, secure or nonsecure}</description>
|
|
<value>#11x</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RO0</name>
|
|
<description>Read-Only Master n</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the ATCn are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the ATCn are ignored.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ATC2</name>
|
|
<description>Attribute Configuration Master n</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>00x</name>
|
|
<description>Master attributes are statically forced to {privileged, secure}.</description>
|
|
<value>#00x</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>010</name>
|
|
<description>Master attributes are statically forced to {user, secure}.</description>
|
|
<value>#010</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>011</name>
|
|
<description>Master attributes are statically forced to {user, nonsecure}.</description>
|
|
<value>#011</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>100</name>
|
|
<description>Enable master attribute {privileged or user} and statically force {secure}.</description>
|
|
<value>#100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>101</name>
|
|
<description>Enable master attribute {privileged or user} and statically force {nonsecure}.</description>
|
|
<value>#101</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>11x</name>
|
|
<description>Enable master attribute {privileged or user, secure or nonsecure}</description>
|
|
<value>#11x</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>RO2</name>
|
|
<description>Read-Only Master n</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Writes to the ATCn are allowed.</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Writes to the ATCn are ignored.</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MMDVSQ</name>
|
|
<description>Divide and Square Root</description>
|
|
<prependToName>MMDVSQ_</prependToName>
|
|
<baseAddress>0xF0004000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x14</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DEND</name>
|
|
<description>Dividend Register</description>
|
|
<addressOffset>0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVIDEND</name>
|
|
<description>Dividend</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSOR</name>
|
|
<description>Divisor Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DIVISOR</name>
|
|
<description>Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<description>Control/Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0x9FFFFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>No operation initiated</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If CSR[DFS] = 1, then initiate a divide calculation, else ignore</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>USGN</name>
|
|
<description>Unsigned calculation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Perform a signed divide</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Perform an unsigned divide</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>REM</name>
|
|
<description>REMainder calculation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Return the quotient in the RES for the divide calculation</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Return the remainder in the RES for the divide calculation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DZE</name>
|
|
<description>Divide-by-Zero-Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Reads of the RES register return the register contents</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else the register contents are returned</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DZ</name>
|
|
<description>Divide-by-Zero</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>The last divide operation had a non-zero divisor, that is, DSOR != 0</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>The last divide operation had a zero divisor, that is, DSOR = 0</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DFS</name>
|
|
<description>Disable Fast Start</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>A divide operation is initiated by a write to the DSOR register</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SQRT</name>
|
|
<description>SQUARE ROOT</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Current or last MMDVSQ operation was not a square root</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Current or last MMDVSQ operation was a square root</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>DIVIDE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>Current or last MMDVSQ operation was not a divide</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>Current or last MMDVSQ operation was a divide</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>BUSY</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>0</name>
|
|
<description>MMDVSQ is idle</description>
|
|
<value>#0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>1</name>
|
|
<description>MMDVSQ is busy performing a divide or square root calculation</description>
|
|
<value>#1</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RES</name>
|
|
<description>Result Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RESULT</name>
|
|
<description>Result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCND</name>
|
|
<description>Radicand Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0</resetValue>
|
|
<resetMask>0</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>RADICAND</name>
|
|
<description>Radicand</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|